Showing papers on "Chip published in 1986"

The Torus Routing Chip

Abstract: The torus routing chip (TRC) is a self-timed chip that performs deadlock-free cut-through routing in k-ary n-cube multiprocessor interconnection networks using a new method of deadlock avoidance called virtual channels. A prototype TRC with byte wide self-timed communication channels achieved on first silicon a throughput of 64Mbits/s in each dimension, about an order of magnitude better performance than the communication networks used by machines such as the Caltech Cosmic Cube or Intel iPSC. The latency of the cut-through routing of only 150ns per routing step largely eliminates message locality considerations in the concurrent programs for such machines. The design and testing of the TRC as a self-timed chip was no more difficult than it would have been for a synchronous chip.

Spread spectrum wireless PBX

Abstract: The present invention relates to a wireless PBX network wherein direct sequence spread spectrum multiple access is used for voice and data communications to support a plurality of local-local and local-external calls. The present wireless PBX arrangement comprises a plurality of local user transceivers using a first separate unique chip sequence patterns for information communication and a second common chip sequence pattern for call-set up; and a central PBX comprising (a) a plurality of PBX transceivers, each of which uses a separate first chip sequence pattern which is matched to a corresponding local user transceiver; (b) a switching means for interconnecting local users to each other or to an external network via the associated PBX transceivers; and (c) a call set-up receiver responsive solely to initial call set-up information sent by any user using the second common chip sequence pattern. Optional selection diversity or equal gain combining diversity and/or error correction encoding may also be included in the transceivers.

Ultrafast All-Optical Synchronous Multiple Access Fiber Networks

Abstract: Two synchronous multiple access schemes, TDMA and CDMA, are proposed for fiber optic networks using optical signal processing. Network synchronization is achieved by using a central modelocked laser which also serves as the source for each station. The data are converted into a high-bandwidth optical signal using electrooptic modulators. The accessing schemes use optical fiber delay lines. The feasibility of these schemes is discussed.

Semiconductor chip mounting system

Abstract: A semiconductor chip module with a flat mounting surface is disclosed. A wafer-scale silicon semiconductor chip is provided with electronic circuits formed therein. The chip has a metallized back face and contacts on the opposite, front face. A solder layer secures the metallized back face of the chip to the mounting surface substantially without voids.

A real-time two-dimensional moment generating algorithm and its single chip implementation

Abstract: We present a fast algorithm and its single chip VLSI implementation for generating moments of two-dimensional (2-D) digital images for real-time image processing applications. Using this algorithm, the number of multiplications for computing 16 moments of a 512 × 512 image is reduced by more than 5 orders of magnitude compared to the direct implementation; the number of additions is reduced by a factor of 4. This also makes the software implementation extremely fast. Using the chip, 16 moments μp,q(p = 0, 1, 2, 3, q = 0, 1, 2, 3) of a 512 × 512 8 bits/pixel image can be calculated in real time (i.e., 30 frames per second). Each moment value is computed as a 64- bit integer. The basic building block of the algorithm is a single-pole digital filter implemented with a simple accumulator. These filters are cascaded together in both horizontal and vertical directions in a highly regular structure which makes it very suitable for VLSI implementation. The chip has been implemented in 2.5 μ CMOS technology, it occupies 6100 μm × 6100 μm of silicon area. The chip can also be used as a general cell in a systolic architecture for implementing 2-D transforms having polynomial basis functions.

A Discrete Fourier-Cosine Transform Chip

Abstract: An 8-point Fourier-cosine transform chip designed for a data rate of 100 Mbits/s is described. The top-down design is presented step by step, including algorithm modification for VLSI suitability, architectural choices, testing overhead, internal precision assignments, mask generation, and finally, verification of the layout. A high-level language (C) design tool was developed concurrently with the layout. This tool allows mimicking exactly the different representations of the algorithm: software, mask, and chip. This provides an automatic cross-checking at all design stages. The VLSI environment created by this tool, as well as existing powerful CAD tools, made a fast design-time possible.

Global position system receiver

Abstract: A Global Position System (GPS) receiver (10/24) is disclosed which includes an RF converter (24) and quadrature digitizer implemented in hardware and a signal processor including a computer (38), code generator (122, 124, 126, 128 or 130) and preprocessor (112,114,116,118 or 120). The preprocessor has a divide by (1, 2, 3) divider (132) for controlling the code generator so as to provide I, Q early, prompt and late digital signals of 0,5 chip separations to the computer for tracking code phase, carrier phase/frequency and signal amplitude. This structure eliminates the need for numerically controlled oscillators implemented in hardware while maintaining accurate performance.

Direct-Sequence Spread-Spectrum Multiple-Access Communications Over Nonselective and Frequency-Selective Rician Fading Channels

Abstract: An accurate approximation is obtained for the average probability of error in an asynchronous binary direct-sequence spreadspectrum multiple-access communications system operating over nonselective and frequency-selective Rician fading channels. The approximation is based on the integration of the characteristic function of the multiple-access interference which now consists of specular and scatter components. For nonselective fading, the amount of computation required to evaluate this approximation grows linearly with the product KN , where K is the number of simultaneous transmitters and N is the number of chips per bit. For frequency-selective fading, the computational effort grows linearly with the product KN2. The resulting probability of error is also compared with an approximation based on the signal-to-noise ratio. Numerical results are presented for specific chip waveforms and signature sequences.

A 1-Mbit DRAM with 33-MHz serial I/O ports

Abstract: High-speed operation, a 33-MHz serial cycle, and a 10-ns serial data access time have been realized by internal serial/parallel conversion circuits, a newly designed I/O controller circuit, new dynamic register circuits, a divided sensing method, and an optimized layout design. The chip is fabricated with a 1.2-/spl mu/m double-level polysilicon and double-level aluminium n-channel MOS process technology. An optimized interlevel insulator realizes equivalent first- and second-level aluminium pitches for a compact chip design. The chip size is 5.88/spl times/11.2 mm/SUP 2/. This memory has high-speed input and output capability as well as random accessibility. These features are suitable for TV and VCR frame-memory-system applications.

Semiconductor laser device.

Abstract: A semiconductor laser device includes a base, a semiconductor laser chip and a resin layer enclosing the semiconductor laser chip. The base may have a monitor photodiode chip mounted thereon in the vicinity of the semiconductor laser chip. The resin layer enclosing the semiconductor laser chipor both of the semiconductor laser chip and the monitor photodiode chip is made of a single synthetic resin having a thickness not greater than 500µm and also having a surface substantially parallel to an outwardly oriented beam emitting end face of the semiconductor laser chip.

Integrated multisensor chip

Abstract: A multipurpose integrated-sensor chip has been fabricated for the simultaneous measurement of physical and chemical variables The multipurpose chip which measures 8 × 9 mm2contains conventional MOS devices for signal conditioning, array accessing, and output buffering along with the following on-chip sensors: a gas-flow sensor, an infrared-sensing array, a chemical-reaction sensor, cantilever-beam accelerometers, surface-acoustic-wave (SAW) vapor sensors, a tactile sensor array, and an infrared charge-coupled device imager The multisensing functions of this chip utilize both the pyroelectdc and piezoelectric effects in ZnO thin films Fabrication of the chip is carried out using a conventional 3-µm Si NMOS process combined with Si micromachining techniques Compatible fabrication technology and sensor properties are described

Electronic clinical thermometer

Abstract: PURPOSE:To make possible the temp. matching while a cap is held removed by disposing adjusting elements for temp. matching near the cap mounting part for exchanging a battery in a circuit board to which an IC chip is packaged. CONSTITUTION:The circuit board 7 packaged with a liquid crystal cell 4 for displaying temp., the IC5, a trimmer resistor 6 for temp. matching, etc., conductive rubber 8 for electrical connection of the board 7 and the cell 4, switching rubber 9 and the battery 10 are housed in a middle frame 3 of an electronic clinical thermometer 1. The cap 2 is fitted to one end 13b of a body case 13. The removal of the cap 2 exposes partly the frame 3 and exposes a hole 3d for adjustment, a notch 3e and inspection holes 3f, 3g, thus permitting the adjustment of the resistor 6 and the contact with an inspection terminal 7b.

VLSI implementation in multiple-valued logic of an FIR digital filter using residue number system arithmetic

Abstract: Computer simulations using SPICE establish the feasibility of implementing a highly pipelined high-speed FIR digital filter using Multiple-Valued Logic (MVL) Read-Only Memories (ROM's) to implement Residue Number System (RNS) Arithmetic in VLSI technology. A single VLSI chip can be used to convert from 8-bit binary to a 16-bit RNS with one additional chip to convert back. The basic approach proposed could be implemented in I^{2}L , MOS, CMOS, or ECL technologies. A detailed design and simulation using ECL technology yields less than 20 000 gates and less than 13-W power dissipation per filter weight. A maximum throughput rate of 30 MHz can be achieved with an ECL design based on partitioning the circuit into 2.5 VLSI chips.per filter weight. A MOS or CMOS design can yield a considerable power savings with a corresponding reduction in throughput rate and number of VLSI chips while an (Integrated Injection Logic) (I^{2} L) design can achieve moderate speed and moderate power consumption with relative/low power supply voltages.

A 12-bit successive-approximation-type ADC with digital error correction

Abstract: A correction algorithm has been implemented that gives an almost twofold improvement in conversion speed without loss of accuracy or changes to the analog circuitry of a slower design. The design of a smart successive-approximation register chip, which has been fabricated in a double poly CMOS process and takes up 18 mil/SUP 2/ in die area, is described. The area is 13% larger than that of an A/D converter utilizing the same analog chip but a conventional digital chip without error correction. A speed improvement from 12 to 7 /spl mu/s was obtained with digital error correction.

Method of making packaged IC chip

Abstract: In the manufacture of a packaged IC chip, a lead frame segment has a plurality of leads, the ends of which are connected to opposing rails. After the leads are secured to a lead frame support, the rails are removed and an IC chip is then connected. The chip and lead frame are then encapsulated between the support and a cover.

Single chip thermal tester

Abstract: A thermal tester for measuring the efficiency of a heat transfer device for cooling semiconductor chips is disclosed having a positioning means operable to position the heat transfer device in thermal contact with the chip. The positioning means is adjustable in at least 5 degrees of freedom. Temperature sensors are provided to sense the temperature of the chip, the chip support substrate and the positioning means adjacent the heat transfer device. Means is provided to dispose the chip and heat transfer device in a vacuum. Control means is also provided to adjust the temperature of the chip unitl it is the same as the substrate to thereby assure heat transfer occurs only from the chip to the positioning means by way of the heat transfer device. When this thermal balance is achieved the thermal resistance of the heat transfer device can be calculated.

Full chip integrated circuit tester

Abstract: Contactless probing of an integrated circuit is carried out by flooding the surface of the integrated circuit with pulsed ultraviolet laser light, causing photoelectron emission as a function of the potentials at micropoints on the integrated circuit, converting this two-dimensional electron pattern into a corresponding relatively long duration pattern of luminescence by a luminescent target, and reviewing the result by video/computer scanning. Separate embodiments allow testing either in vacuum or in air, with or without insulating passivation layers present on the chip. The result is a contactless oscilloscope which monitors instantaneous voltages (logic states and AC switching waveforms) for a full two-demsnsional array of micropoints simultaneously. A chip with test points and appropriate windows for laser activation and luminescent targeting can be specially designed for optimal testing.

MISFET with input amplifier

Abstract: A power FET is preceded by an input amplifier consisting of a second FET of the same channel type and a third FET of an opposite channel type. The FETs of the pre-amplifier can be integrated into the chip of the power FET without additional production steps if the power FET and the second FET are designed as vertical FETs and the third FET as a lateral FET. Through this semiconductor device, the relatively high input capacitance of power MISFETs, which results in slow switching speeds when driven by standard ICs, is overcome.

A 4-Mbit DRAM with half-internal-voltage bit-line precharge

Abstract: A single 5-V supply 4-Mb dynamic random access memory (DRAM) was developed by using a buried-storage-electrode memory cell, a half-internal-voltage bit-line precharge method combined with a constant voltage converter, and a high signal-to-noise ratio sensing scheme. The chip was designed in a double-polycide, single-Al, epitaxial substrate NMOS technology with a 0.8-/spl mu/m minimum design rule. As a result, a 4M word/spl times/1-bit DRAM with 95-ns typical access time and 99.2-mm/SUP 2/ chip area was attained by 10.58-/spl mu/m/SUP 2/ storage cells.

Logic-circuit layout for large-scale integrated circuits

Abstract: A VLSI chip (100) has multiple annular rings (122) of circuit cells, interspersed with annular wiring channels (123) for interconnecting the cells. Another wiring layer runs perpendicular to the rings. A central chip area (110) contains all the I/O connections (113) for the chip.

Characteristics of Prototype CMOS Quaternary Logic Encoder-Decoder Circuits

Abstract: The use of quaternary logic input and output signals for delivering information on and off chip could reduce the number of required package pins or increase the amount of information conveyed on a fixed number of package pins. In this correspondence, we discuss the performance of prototype CMOS binary-to-quaternary encoder and quaternary-to-binary decoder test circuits that have been realized on a gate array IC chip.

Advanced single-chip signal processor

Abstract: A CMOS single chip signal processor, which has 32-bit floating point arithmetic units and large capacity on-chip memories, has been developed. The processor, having a floating point parallel multiplier, a floating point accumulator, two 512- word data RAMs, a 1024-word data ROM and a 2048- word program ROM, is implemented within a 15.4 × 8.4 mm chip area, containing 370,000 elements. As the processor is designed to perform highly accurate multiply-accumulate operations for digital filtering and to attain complex addressing capability for FFT computation, this processor can execute FIR computation at the 150 nsec per tap rate, as well as achieve 1024 point complex FFT computation in 12.3 msec.

Logic array chip

Abstract: A programmable logic array chip is provided with an auxiliary grid pattern of conductive paths. Connecting elements can be selectively activated to connect certain ones of the auxiliary paths to the normal grid pattern paths which are connected to functional elements. In such manner, it is possible to provide a logic array chip that has increased flexibility in terms of user programmable functions.

Semiconductor integrated circuit devices and methods for testing same

Abstract: A semiconductor integrated circuit device, comprises a semiconductor integrated circuit chip having a plurality of signal wires and a plurality of test terminals connected to said signal wires. The test terminals are concentrated in at least one selected circuit area of the semiconductor integrated circuit chip to permit chip diagnosis using an image mode electron beam detector.

VLSI- A to D and D to A converters with multi-stage noise shaping modulators

Abstract: High resolution oversampling analog-to-digital and digital-to-analog converters are proposed. These converters utilize novel multi-stage noise shaping modulation techniques which can be implemented with fine pattern MOS technology. The modulators consist of multi-connected delta sigma modulation loops with single integration. The quantization noise in the first loop is re-quantized by the second loop. That is, the noise is canceled by adding the second loop output signals to the first loop output. The resolution of the modulators increases in proportion to the number of stages and there are no feedback-loop stability problems. An experimental prototype chip is fabricated using 1.5µm CMOS technology. This chip achieves a wide dynamic range of 88dB at a baseband of 3.4KHz and sampling rate of 2.048MHz. This dynamic range corresponds to a 14-bit equivalent resolution.

Computer Generation of Digital Filter Banks

Abstract: In order to reduce the design time of digital filter bank circuits, a design system has been developed. The software consists of the filter compiler which converts high level filter descriptions to hardware descriptions and the layout generator which converts the hardware descriptions to a layout file. To verify the algorithms before fabrication, a test system is employed. The development time of this system was kept to a minimum by designing the hardware to be easily micro coded and assembled. Several circuits have been fabricated and tested that were generated with this system, including a single bandpass filter chip, a 112-pole 16-channel filter bank for a speech recognition system and a 16-channel spectrum analyzer for consumer stereo applications. The speech recognition chip achieved a SNR of 80 dB with an area of 25 mm /sup 2/ in a 4-micron NMOS technology.

A single chip video rate 16×16 discrete cosine transform

Abstract: The Discrete Cosine Transform [1] is a good but computation consuming first step of many image coding and compression algorithms for good quality, low rate transmissions. A low-cost implementation of a high-speed DCT operator would lower the price of CODEC and could open new fields of applications for DCT in real time image processing. This paper presents a one chip operator, achieving a full 16 × 16 DCT computation at video rate. Algorithmic, architectural and implementation choices combined with a careful optimization of the layout have made it possible to design a reasonnable size chip exhibiting such high performance.