Showing papers on "Clock generator published in 2014"

A Fully Self-Contained Logarithmic Closed-Loop Deep Brain Stimulation SoC With Wireless Telemetry and Wireless Power Management

Abstract: Although closed-loop deep brain stimulation (DBS) promises treatment of many neurological disorders, an implantable system-on-chip (SoC) implementing an effective closed-loop DBS algorithm has not been demonstrated. This work introduces a logarithmic, closed-loop DBS system that detects and processes low-frequency brain field signals to control and adapt stimulation currents. The system records and processes neural signals with four low-noise neural amplifier (LNA) channels, a multiplexed logarithmic ADC, and two high-pass and two low-pass digital logarithmic filters. Logarithmic processing saves power and achieves high dynamic range. A logarithmic domain digital signal processor (DSP) and PI-controller controls eight current stimulator channels and enables closed-loop stimulation. An RF transceiver, a clock generator, and a power harvester are also included in the system to achieve a complete implantable SoC. The 4 mm 2 180 nm CMOS prototype consumes a total of 468 μW for recording and processing neural signals, for stimulation, and for two-way wireless communication.

Method and apparatus for source-synchronous signaling

Abstract: A low-power, high-performance source-synchronous chip interface which provides rapid turn-on and facilitates high signaling rates between a transmitter and a receiver located on different chips is described in various embodiments. Some embodiments of the chip interface include, among others: a segmented “fast turn-on” bias circuit to reduce power supply ringing during the rapid power-on process; current mode logic clock buffers in a clock path of the chip interface to further reduce the effect of power supply ringing; a multiplying injection-locked oscillator (MILO) clock generator to generate higher frequency clock signals from a reference clock; a digitally controlled delay line which can be inserted in the clock path to mitigate deterministic jitter caused by the MILO clock generator; and circuits for periodically re-evaluating whether it is safe to retime transmit data signals in the reference clock domain directly with the faster clock signals.

11.4 A 1.5mW 68dB SNDR 80MS/s 2× interleaved SAR-assisted pipelined ADC in 28nm CMOS

Abstract: The resolution and sampling speed of recently reported SAR ADCs have increased to 11+ ENOB at 50 to 100MS/s [1,2]; however, power efficiency has unfortunately suffered when compared to lower-resolution, lower-speed ADCs. This design targets the same high speed and resolution while simultaneously achieving power efficiency previously associated only with low-speed, low-resolution ADCs. Furthermore, the power reported includes the consumption from the active reference generator, clock generator and encoder (since this is an industrial SoC), differentiating it from the majority of reported SAR ADCs. A dynamic residue amplifier with excellent noise-filtering properties, embedded in a pipelined architecture, is a key power-saving technique. In addition, an energy-efficient switched-capacitor (SC) DAC is obtained by using a small fraction of the total DAC capacitance during the initial SAR steps. The realized Walden FOM is 9.1fJ/conv-step while the Schreier FoM is 172.3dB, currently the highest reported number to date for sampling speeds greater than 0.1Ms/s, based on the extensive list of recent data converters compiled in [3].

System and method for an accuracy-enhanced dll during a measure initialization mode

Abstract: A clock generator having a delay locked loop and a delay control circuit. The delay locked loop receives an input clock signal and adjusts an adjustable delay circuit to generate an output clock signal that is synchronized with received input clock signal. The delay control circuit coupled to the delay locked loop generates a control signal to initialize the delay measure operation to adjust the adjustable delay circuit, after comparing the phase difference of the input clock signal and the output clock signal. The delay control circuit further generates a start measure control signal to start measuring a delay applied to the measurement signal propagating through the adjustable delay circuit, and generates a stop measure control signal to stop the delay measurement of the measurement signal. The delay adjustment of the delay locked loop is then adjusted to apply the delay measurement when synchronizing the input and output clock signals.

Layout Synthesis and Loop Parameter Optimization of a Low-Jitter All-Digital Pixel Clock Generator

Abstract: This paper presents a dual-loop ADPLL suitable for video pixel clock generation. The dual-loop architecture where a fast subloop works as a DCO inside a main loop is chosen since it can efficiently suppress the ring oscillator phase noise. In order to satisfy a wide tuning range and fine resolution requirements in the pixel clock PLL, the TDC and DCO with two-step and bottom-up control are employed. An s-domain model is utilized to tune the loop parameters so that the dual-loop PLL has the optimum jitter performance. The measurement results match well with the proposed s-domain model and clearly show the effectiveness of the dual loop in suppressing the phase noise of the DCO. We propose a new cell-based layout technique to avoid performance degradation during automatic placement and routing, which is compatible with the conventional digital design environment. A chip that occupies 0.032 mm2 has been fabricated in the 28-nm CMOS technology. The synthesized DCO shows 1.7-LSB DNL which is close to a full-custom layout. The rms integrated jitter is only 15 ps at 250 MHz, even though PLL operates at the extremely low input frequency of 100 kHz. Power consumption is 3.1 mW at 250 MHz with a 1.0-V supply.

High efficient control circuit for buck-boost converters and control method thereof

Abstract: A controller used in a buck-boost converter includes a clock generator, an error amplifying circuit, a comparing circuit, a proportional sampling circuit, a logic circuit, a pulse width increasing circuit, first and second driving circuits. Based on a clock signal generated by the clock generator, the proportional sampling circuit samples the difference between a current sensing signal and a compensation signal generated by the error amplifying circuit, and generates a proportional sampling signal. The pulse width increasing circuit generates a sum control signal based on the proportional sampling signal and a logic control signal generated by the logic circuit, wherein a modulation value adjusted by the proportional sampling signal is added to the pulse width of the logic control signal to generate the pulse width of the sum control signal. The first and second driving circuits generate driving signals based on the sum control signal and the logic control signal.

On-Chip Photovoltaic Energy Conversion in Bulk-CMOS for Indoor Applications

Abstract: Modeling and design aspects of on-chip photovoltaic energy conversion, voltage boosting and storage in bulk CMOS are investigated under the constraints of indoor illumination and small form factor. A power-supply architecture consisting of a photovoltaic converter, a clock generator, a charge-pump and a storage capacitor is considered. Maximization of the recharging rate of the capacitor at the low end of irradiance is adopted as the aim of design optimization. First, photodiodes available for conversion in bulk CMOS are comparatively evaluated, and potentially the most efficient ones are experimentally characterized for the typical range of indoor irradiance. Next, a generic model is developed and experimentally verified for a clock generator powered by a converter built with these photodiodes. This is followed by the modeling and experimental verification of a Dickson charge-pump whose single-device rectifier is free of body effect and near-ideal in forward characteristic. These models are based on the subthreshold operation of devices as necessitated by optimization under the limitations of bulk-CMOS stacking and indoor irradiance. Guidelines for design optimization are derived from these models. Experimental work is based on two test chips fabricated in 0.18- μm bulk CMOS with deep n-well option.

20.4 A fully integrated single-chip 60GHz CMOS transceiver with scalable power consumption for proximity wireless communication

Abstract: A fully-integrated single-chip CMOS transceiver with MAC and PHY for 60GHz proximity wireless communication is presented. A 60GHz wireless communication single-chip transceiver has not yet been reported due to large power consumption issues. However, by limiting the application to high-throughput proximity transmission, thermal issues arising in a single-chip have been overcome. A 2GHz broadband OFDM single-chip transceiver suffers from SNR degradation due to the reference clock (REFCLK) and baseband clock (BBCLK) spurs in RF/analog circuits. Low frequency spurs in the clock generator (CLKPLL) due to the mixing of the ADC/DAC sampling clock (SCLK) and other clocks such as REFCLK and BBCLK have been eliminated by careful frequency planning of those clocks. In addition to that, spur suppression in digital baseband and noise-tolerant RF/analog circuit designs are employed. The spurs have been successfully suppressed to less than -35dBc. The chip achieves a PHY data-rate of 2.35Gb/s and MAC throughput of 2.0Gb/s at a distance of 4cm. Power consumption is scalable to the throughput by the introduction of fast Sleep and Awake modes. The average power consumption at a throughput of 0.2Gb/s is reduced to 36% of that at 2.0Gb/s.

A 2.9mW, +/− 85ppm accuracy reference clock generator based on RC oscillator with on-chip temperature calibration

Abstract: A novel on-chip frequency calibration of temperature dependency is proposed for CMOS reference frequency generator. High-order temperature coefficients are rapidly extracted by employing a carefully designed on-chip heater, so that the frequency deviation due to the temperature variation is accurately estimated, and compensated in digitally by means of all-digital PLL (ADPLL). The proposed technique was implemented in a 0.18um CMOS and achieved ±85ppm accuracy at 24MHz, consuming a power of 2.9mW.

A 6-bit 1-GS/s Two-Step SAR ADC in 40-nm CMOS

Abstract: This brief presents a single-channel two-step successive approximation register (SAR) analog-to-digital converter (ADC) using a source follower as an interstage residue amplifier. An asynchronous SAR ADC with two-step timing can effectively allocate the bit-resolving procedure into the whole clock period and eliminate a dedicated duty-cycle clock generator. The arbitrary weight capacitor array technique is utilized to tolerate offset mismatch between the coarse and fine stages. The level-shift technique is used to accelerate the comparator. The ADC in 40-nm CMOS obtains 5.6 and 4.9 effective numbers of bits at Nyquist with the conversion rate of 800 MS/s and 1 GS/s, respectively. It consumes 5.3 mW at 1 GS/s and achieves a figure of merit of 180 fJ/conversion-step. The core circuit occupies an area of 0.009 $\hbox{mm}^{2}$ .

A 2GHz-to-7.5GHz quadrature clock-generator using digital delay locked loops for multi-standard I/Os in 14nm CMOS

Abstract: A highly digital quadrature clock generator using a digital DLL that employs a digital loop filter and digitally-calibrated replica-based regulator is presented. The proposed DLL combines the advantages of both analog and digital loop-filters of conventional architectures to implement a wide-range, energy efficient, highly digital, and high performance quadrature clock generator. To suppress supply-noise, we propose an LDO that combines fast/slow paths with a replica-load to achieve better than 20dB rejection with small area and low power. Fabricated in Intel's 14nm CMOS process, the proposed digital DLL operates over a wide range of output frequencies (2GHz-to-7.5GHz). At 7GHz, it achieves 176fs rms /2.7ps pp long-term jitter while consuming 4.4mW. The DLL is 4X smaller than state-of-the art designs and occupies an active area of 0.0024mm 2 .

A 1.9 GS/s 4-bit sub-Nyquist flash ADC for 3.8 GHz compressive spectrum sensing in 28 nm CMOS

Abstract: Spectral activity detection in wideband radio-frequency (RF) signals for cognitive-radio applications typically necessitates expensive and energy-inefficient analog-to-digital converters (ADCs). In this paper, we present a novel compressive sensing (CS)-based analog front-end, which is able to sample sparse wideband RF signals at low cost and low power. The analog front-end consists of a pseudo-random non-uniform clock generator unit offering the possibility to configure the (average) undersampling factor at run-time, and a low-cost, wideband 1.9GS/s 4bit flash ADC. The spectral information acquired at sub-Nyquist rates can be recovered off-line via a novel sparse signal dequantization algorithm. The developed analog front-end is implemented in 28nm CMOS, and enables the recovery of spectrally sparse RF signals up to 3.8GHz by means of CS, which corresponds to a Nyquist-equivalent sampling rate of 7.6GS/s. The ADC and pseudo-random clock generator together occupy less than 0.1mm2, and consume an estimated 4.1mW to 5.4mW for undersampling factors between 4 and 11.5.

Energy efficient acquisition and reconstruction of EEG signals

Abstract: In Wireless Body Area Networks (WBAN) the energy consumption is dominated by sensing and communication. Previous Compressed Sensing (CS) based solutions to EEG tele-monitoring over WBAN's could only reduce the communication cost. In this work, we propose a matrix completion based formulation that can also reduce the energy consumption for sensing. We test our method with state-of-the-art CS based techniques and find that the reconstruction accuracy from our method is significantly better and that too at considerably less energy consumption. Our method is also tested for post-reconstruction signal classification where it outperforms previous CS based techniques. At the heart of the system is an Analog to Information Converter (AIC) implemented in 65nm CMOS technology. The pseudorandom clock generator enables random under-sampling and subsequent conversion by the 12-bit Successive Approximation Register Analog to Digital Converter (SAR ADC). AIC achieves a sample rate of 0.5 KS/s, an ENOB 9.54 bits, and consumes 108 nW from 1 V power supply.

Ultra wide band hopping frequency synthesizer based on digital up-conversion

Abstract: The invention discloses an ultra wide band hopping frequency synthesizer based on digital up-conversion. The ultra wide band hopping frequency synthesizer based on digital up-conversion comprises a PC, a field-programmable gate array ( FPGA ), a clock generator, a DA converter and a low-pass filter, wherein a hopping frequency sequence storer, a hopping frequency carrier signal generating unit, a modulation base band interpolation filtering unit and an up-conversion unit are arranged in the FPGA, the hopping frequency sequence storer is connected with the hopping frequency carrier signal generating unit through a signal line, and the hopping frequency carrier signal generating unit and the modulation base band interpolation filtering unit are connected with the up-conversion unit through two signal lines respectively. According to the ultra wide band hopping frequency synthesizer based on digital up-conversion, a digital base band is directly modulated onto a carrier wave by means of digital up-conversion, and then hopping frequency signals modulated by any digits are generated, hopping frequency bandwidth reaches 800MHz, modulation bandwidth is larger than 100MHz, and carrier wave leakage and IQ imbalance are avoided.

Clock generator using free-running oscillator and method therefor

Abstract: A clock generator comprises a free-running oscillator and a tunable frequency synthesizer. The free-running oscillator has an output for providing an oscillator clock signal. The tunable frequency synthesizer is coupled to the free-running oscillator and provides a clock output signal in response to the oscillator clock signal and a frequency control signal. The frequency control signal corresponds to a measured characteristic of the free-running oscillator.

Current-mode electronically-tunable Schmitt Trigger using single 65nm ±0.75V CMOS CDTA

Abstract: A current-mode electronically-tunable Schmitt Trigger circuit is presented. The analog building block used is a new Multiple-Output CDTA (MO-CDTA) which is designed and implemented at 65 nm CMOS technology node. The proposed circuit employs only a single MO-CDTA and no passive components thereby making it attractive for integration. The operation of the proposed Schmitt Trigger was verified by using SPICE simulations. Electronic tunability of the hysteresis characteristics was also explored with good results. A simple application of the proposed Schmitt Trigger, in the form of a current-mode clock generator is also presented.

Laser system and extreme ultraviolet light generation system

Abstract: The laser system may include: a clock generator; a mode-locked laser device having an optical resonator; a controlling device capable of controlling resonator length of the optical resonator; a detector disposed in an optical path of the pulse laser beam, configured to detect the pulse laser beam and output a detection signal; a switching device disposed in the optical path of the pulse laser beam, capable of switching the pulse laser beam; and a controller, capable of controlling the controlling device based on the clock signal outputted by the clock generator and on the detection signal outputted by the detector, and capable of controlling the switching device based on the clock signal outputted by the clock generator and on a timing signal outputted by an external device.

Device for controlling a switching mode power supply

Abstract: The present invention relates to a device for controlling a switching mode power supply, which regulates the switching duty ratio to control the output voltage of a switching mode power supply (SMPS). A comparator outputs different state signals according to the result of the comparison between the output voltage of the SMPS with a reference voltage. A clock generator generates the operating frequency of an internal chip and the switching frequency of the SMPS. A digital control unit determines the turning on/off of a current cell depending on the state signals input from the comparator. A digital pulse width modulator determines the charging/discharging time of an internal capacitor on the basis of the amount of current by the current cell in order to determine the duty ratio of a digital pulse width modulating signal.

Characterization and Modeling of the Conducted Emission of Integrated Circuits Up To 3 GHz

Abstract: In this paper, an electrical model in order to predict the electromagnetic compatibility (EMC) conducted emission of integrated circuits (ICs) up to 3 GHz is presented. The electrical model predicts the behavior of the propagation paths of electromagnetic conducted emissions at high frequency by including all distributed effects and capacitive and inductive couplings. The proposed model has been compared with the standard IC emission model (ICEM-CE) to predict the EMC of a clock generator by means of the feature selective validation (FSV) method. The results show that the proposed model can expand the frequency range up to 3 GHz with a high degree of accuracy. Moreover, an alternative approach to model the electromagnetic noise that is based on the analysis of its spectral components is proposed.

Multi-phase clock generation

Abstract: Embodiments are disclosed that relate to multi-phase clock generators and data samplers for use in high speed I/O circuitry. One disclosed example provides a multi-phase clock generator including a delay line having a plurality of delay elements, the delay line being configured to receive an input clock signal and output a plurality of output clock signals having different phases compared to a phase of the input clock signal. The multi-phase clock generator further includes a control circuit configured to control the delay line based at least in part upon rising edges and falling edges of one or more output clock signals output at one or more locations along the delay line.

Edge generator-based phase locked loop reference clock generator for automated test system

Abstract: An automatic test system configured for generating a periodic signal of a programmable frequency. The automatic test system may comprise a clock, an edge generator coupled to the clock, a phase locked loop, and a delay adjustment circuit. The edge generator may comprise an edge generator output, an enable input and a delay input. The edge generator may produce at the edge generator output a signal with a delay relative to an edge of the clock specified by a value at the delay input in each cycle of the clock for which the enable input is asserted. The phase locked loop may comprise a reference input and a phase locked loop output configured to provide the periodic signal of the programmable frequency. The delay adjustment circuit may comprise an accumulator that may increase in value by a programmed amount for each cycle of the clock.

Programmable fractional-ratio frequency multiplying clock generator

Abstract: A new programmable delay-locked loop (DLL) based fractional frequency multiplying clock generator is presented. In contrast to conventional DLL-based clock generators that generate only integer clock multiplication, the proposed clock generator provides fractional-ratio frequency multiplication while maintaining the advantages of DLLs, such as the deskewing between the input and the output clocks. Implemented in a 0.13 μm 1.2 V CMOS process, the proposed clock generator achieves an effective peak-to-peak jitter of 7.5 ps and occupies an active area of 0.018 mm 2 while dissipating 9.0 mW at 1.5 GHz. The output frequency ranges from 0.85 to 1.5 GHz with programmable fractional multiplication ratios of N / M , where N = 4, 5, 8, 10 and M = 1, 2, 3.

Multifunctional programmable signal generating parameter testing system

Abstract: A multifunctional programmable signal generation parameter testing system is provided; a system on chip substrate or a same system level packaged circuit substrate is provided with a central processor, a memory, a clock generator, and a programmable control signal generation source system, a data acquisition system, a digital signal processor, and a function circuit real time selection control module; the programmable control signal generation source system is used for generating a set waveform voltage excitation signal according to a control indication in the memory; the function circuit real time selection control module controls a signal generation module according to the selection control indication of the central processor so as to output a testing signal exciting an external tested object; the data acquisition system uses a modularized combined multi-functional parameter test module in the function circuit real time selection control module so as to collect a stress reaction simulation electric signal of the external tested object, and the stress reaction simulation electric signal is converted into a stress reaction digital signal; the digital signal processor can fast process the stress reaction digital signal generated in the data acquisition system in real time; the function circuit real time selection control module can select and control the multi-functional parameter test module in real time; the multifunctional programmable signal generation parameter testing system can improve the reliability of the testing system under a high frequency high speed test condition, improves anti-electromagnetic interference effect, realizes multifunctional height cooperation test measurement, and reduces cost and land occupation space.

Clock spurs reduction technique

Abstract: Aspects of the disclosure provide a circuit having a jittered clock generator. The jittered clock generator is configured to add jitter of a controlled characteristic to a first clock signal of a clock frequency to generate a second clock signal to be used by a transceiver for operating at a radio frequency. The jitter of the controlled characteristic adjusts a clock harmonic at the radio frequency of the transceiver.

A 1.2 – 6.4 GHz clock generator with a low-power DCO and programmable multiplier in 40-nm CMOS

Abstract: This paper presents a clock generator for a MIPI M-PHY serial link transmitter, which includes an ADPLL, a digitally controlled oscillator (DCO), a programmable multiplier, and the actual serial driver. The paper focuses on the design of a DCO and how to enhance the frequency resolution to diminish the quantization noise introduced by the frequency discretization. As a result, a 17-kHz DCO frequency tuning resolution is demonstrated. Furthermore, implementation details of a low-power programmable 1-to-2-or-4 frequency multiplier are elaborated. The design has been implemented in a 40-nm CMOS process. The measurement results verify that the circuit provides the MIPI clock data rates from 1.248 GHz to 5.83 GHz. The DCO and multiplier unit dissipates a maximum of 3.9 mW from a 1.1 V supply and covers a small die area of 0.012 mm 2 .

Register-free asynchronous successive approximation analog-to-digital converter

Abstract: The invention provides a register-free asynchronous successive approximation analog-to-digital converter which includes a digital-to-analog converter used for obtaining a pair of differential input signals; a comparator used for comparing the pair of differential input signals so as to obtain a comparison result; a logic switch controller used for generating a first control signal according to the comparison result and a second control signal used for changing voltage amplitudes of capacitor lower polar plates in capacitor arrays of the digital-to-analog converter and then changing amplitudes of the pair of differential input signals and storing the comparison result; an asynchronous clock generator used for generating an asynchronous clock signal, which drives the comparator to work, according to the comparison result and the first control signal; and an output device used for outputting the comparison result stored in the logic switch controller when receiving a first externally supplied clock signal. The register-free asynchronous successive approximation analog-to-digital converter obviously improves the conversion speed and work efficiency of an analog-to-digital converter.

System and method for synchronizing local oscillators

Abstract: Provided is a method and apparatus for aligning a first local oscillator (LO) clock generated by a controllable LO clock generator in a first radio frequency (RF) path with a second LO clock in a second RF path. The apparatus includes a synchronization channel configured to exchange a synchronization clock between the first and second RF paths, a phase detector configured to measure a phase alignment between the first and second LO clocks, and a loop filter configured to drive the controllable LO clock generators using the phase alignment. Also provided is a time to digital converter. The time to digital converter includes a D flip-flop for sampling first and second input clocks with a third clock, and a counter configured to synchronously increment the resulting samples and create a digital proportional value representing the delay between the first and second clocks.

Phase locked loop circuit

Abstract: The present disclosure provides a clock generator circuit comprising a master clock generator unit configured to generate a master clock signal, and a plurality of slave phase locked loop units. Each of the plurality of slave phase looked loop units is configured to receive the master clock signal as an input reference signal and a corresponding source clock signal. The slave phase locked loop unit may comprise an inner loop and an outer loop. The inner loop may comprise a frequency synthesizer locked on a master clock signal received from a master clock generator unit, while the outer loop may comprise a binary phase detector, an output of which goes to a loop filter with proportional and integral action, controlling the inner loop frequency value via a sigma delta input.