Showing papers on "CMOS published in 1982"

High-speed compact circuits with CMOS

Abstract: Characteristics of various CMOS and NMOS circuit techniques are described, along with the shortcomings of each. Then a new circuit type, the CMOS domino circuit is described. This involves the connection of dynamic CMOS gates in such a way that a single clock edge can be used to turn on all gates in the circuit at once. As a result, complex clocking schemes are not needed and the full inherent speed of the dynamic gate can be utilized. The circuit is most valuable where gates are complex and have high fan-out such as in arithmetic units. Examples are shown of the use of domino circuits in an 8-bit ALU, where simulations indicate a speed advantage of 1.5 to 2 over traditional circuits, and in a 32-bit ALU where a worst case add in 124 ns was projected and a time less than 100 ns was achieved.

MOS operational amplifier design-a tutorial overview

Abstract: Presents an overview of current design techniques for operational amplifiers implemented in CMOS and NMOS technology at a tutorial level. Primary emphasis is placed on CMOS amplifiers because of their more widespread use. Factors affecting voltage gain, input noise, offsets, common mode and power supply rejection, power dissipation, and transient response are considered for the traditional bipolar-derived two-stage architecture. Alternative circuit approaches for optimization of particular performance aspects are summarized, and examples are given.

A precision variable-supply CMOS comparator

Abstract: Several new techniques are presented for the design of precision CMOS voltage comparator circuits which operate over a wide range of supply voltages. Since most monolithic A/D converter systems contain an on-chip voltage reference, techniques have been developed to replicate the reference voltage in order to provide stable supply-independent DC bias voltages, and controlled internal voltage swings for the comparator. These techniques are necessary in order to eliminate harmful bootstrapping effects which can potentially occur in all AC coupled MOS analog circuits. An actively controlled biasing scheme has been developed to allow for differentially autozeroing the comparator for applications in differential A/D converter systems. A general approach for selecting the gain in AC-coupled gain stages is also presented. The comparator circuit has been implemented in a standard metal-gate CMOS process. The measured comparator resolution is less than 1 mV, and the allowable supply voltages range from 3.5 to 10 V.

Floating voltage-controlled resistors in CMOS technology

Abstract: A method for implementing floating voltage-controlled resistors in CMOS technology is proposed. The method takes advantage of the cancellation of the first-order nonlinearities of two MOS transistors in physical proximity.

Titanium disilicide self-aligned source/drain + gate technology

Abstract: Silicides have been used to lower the resistance of gate level interconnects. Recently silicidation of source/drain diffusions have also been reported. In scaled CMOS devices, silicidation of source/drains is particularly important in reducing the sheet resistance of p+ source/drain diffusions. In this paper, a novel technique is described in which TiSi 2 is formed self-aligned to both source/drain and gate regions. Both n and p-channel MOSFETs Silicided with self-aligned TiSi 2 on source/drains gates have been fabricated using this technique. Sheet resistances below 5 Ω/□ on both gate and source/drain levels have been achieved and thus represent at least a 10X reduction in the resistance of p+diffusions. Diode leakage, subthreshold leakage, and threshold voltage measurements on silicided devices are comparable to that of control devices without silicidation, CMOS circuit applications of this TiSi 2 self-aligned source/drain and gate technology are discussed.

Error Analysis and Prevention of Cosmic Ion-Induced Soft Errors in Static CMOS RAMs

Abstract: Cosmic ray interactions with memory cells are known to cause temporary, random, bit errors in some designs. The sensitivity of polysilicon gate CMOS static RAM designs to logic upset by impinging ions has been studied using computer simulations and experimental heavy ion bombardment. Results of the simulations are confirmed by experimental upset cross-section data. Analytical models have been extended to determine and evaluate design modifications which reduce memory cell sensitivity to cosmic ions. A simple design modification, the addition of decoupling resistance in the feedback path, is shown to produce static RAMs immune to cosmic ray-induced bit errors.

Monolithic CMOS low power digital level shifter

Abstract: A CMOS digital level shifter circuit is provided which latches one transistor of a complementary transistor pair off when the other transistor of the pair is on to prevent direct current dissipation of power when the input signals to the shifter circuit are not in transition.

Single Event Error Immune CMOS RAM

Abstract: A technique involving resistive decoupling has been developed and applied to the memory cells of a 1024-bit CMOS static RAM to provide immunity to single event upset by cosmic rays. Doped polysilicon resistors were inserted in the inverter-pair cross-coupling lines of an existing memory-cell design with negligible effect on the device operating characteristics. Computer simulations, as well as laboratory tests with energetic krypton ions, imply the effectiveness of this approach to solving the single event upset problem in satellites. This technique is expected to be applicable to other devices of this type, including those with higher levels of integration.

CMOS LSI and VLSI chips having internal delay testing capability

Abstract: A CMOS LSI or VLSI integrated circuit chip includes a shift register circuit that provides internal delay testing capability. The shift register circuit is disposed around the periphery of the chip and includes a large number of serially connected stages. One mode of operation allows a data signal to pass through the shift register circuit at a speed limited only by the propagation delays associated with the individual stages thereof. In this mode of operation, one net inversion is introduced into the data path and the output of a final stage of the shift register circuit is coupled to the input of a first stage of the shift register circuit, thereby creating a ring oscillator. The period of oscillation of this ring oscillator represents a measure of the average propagation delay times associated with the various circuit elements employed within the LSI or VLSI circuitry. Such delay measurements can readily be made at any level of packaging or system operation.

Circuit for interfacing with both TTL and CMOS voltage levels

Abstract: A voltage compatible circuit for providing TTL and CMOS level inputs and/or outputs is provided. An input signal level detection portion generates either a CMOS or a TTL mode signal in response to a voltage level selection signal. One or more input buffers and/or output buffers is coupled to the CMOS and TTL mode signals. The input buffers are responsive to input signals within predetermined CMOS voltage levels in response to a voltage level signal having at least a predetermined value determined by the input signal level detection portion and within predetermined TTL voltage levels otherwise. The output buffers provide output signals within predetermined CMOS voltage levels in response to a voltage level signal having at least a predetermined value determined by the input signal level detection portion and within predetermined TTL voltage levels otherwise. A reference voltage portion and a bias generator portion are coupled to the input and output buffers to provide the predetermined voltage levels.

Method of making CMOS by twin-tub process integrated with a vertical bipolar transistor

Abstract: A process for forming high performance npn bipolar transistors in an enhanced CMOS process using only one additional mask level. The bipolar transistor is formed using a low dose blanket implant to form the base in the substrate n-well, then applying arsenic-implanted polysilicon to form the emitter. The emitter formation involves forming a blanket polysilicon layer over the wafer, then using the additional photomask to confine the subsequent arsenic implant to the emitter, n + and polysilicon contact regions, prior to application of aluminum metallization. The arsenic implanted polysilicon technique provides state-of-the-art bipolar processing as well as improved contact characteristics. The combined polysilicon-aluminum metallization improves step coverage, circuit reliability, and reduces the possibility of aluminum diffusion (spiking) through junctions. The n-type contact resistance is improved by virtue of being implanted with arsenic; the p-type contact resistance is controlled by the diffusion from the p + regions which dope the polysilicon during the emitter drive-in cycle.

Micropower switched capacitor biquadratic cell

Abstract: The implementation of the double correlated sampling noise reduction technique in conventional strays-insensitive switched capacitor biquad building blocks is described. The function is performed by an offset cancellation circuit which is incorporated into the structure without the use of any additional capacitor, only minor modifications in the switching topology, and one supplementary clock phase. Consequently, a significant reduction of the low-frequency (1/f) noise is made possible and the usual differential amplifiers may be replaced by simple inverting amplifiers operated in class AB, featuring high-speed, low-quiescent power dissipation and low noise. An experimental micropower SC biquadratic filter section designed for `leapfrog' or `follow-the-leader feedback' structures has been developed using high gain (>80 dB) CMOS push/pull inverting amplifiers together with a three-phase clocking sequence. The integrated circuit, implemented in a low-voltage Si-gate CMOS process, achieves excellent accuracy and less than 5 /spl mu/W power dissipation with a 32 kHz sampling rate and /spl plusmn/1.5 V supplies; dynamic range is 66 dB.

Modeling Latch-Up in CMOS Integrated Circuits

Abstract: Latch-up is a common problem in CMOS integrated circuits. The modeling of latch-up with circuit simulation programs is addressed in this paper. The general features of a lumped element latch-up model are discussed along with a step-by-step approach to the component determination of the model. An example is presented to show the value of the latch-up model in latch-up threshold prediction. Finally, some latch-up control methods are discussed.

Effect of CMOS Miniaturization on Cosmic-Ray-Induced Error Rate

Abstract: As device feature size is scaled down for Very Large Scale Integration (VLSI) and Very High Speed Integrated Circuit (VHSIC) applications, consideration must be given to potential increased vulnerabiliity to single particle induced upset (memory soft error or processor logic error) from the natural radiation environment. This paper describes a detailed computer aided modeling study to predict the effect of scaling on the single event upset rate in CMOS memory cells in the galactic cosmic ray environment typical of high altitude satellite orbits.

CMOS Circuit with reduced power dissipation and a digital data processor using the same

Abstract: In an information processor employing a CMOS circuit comprising a first inverter constructed of CMOS field effect transistors and performing a dynamic operation in response to clock signals, and a second inverter which receives an output from the first inverter and which is also constructed of CMOS field effect transistors, the supply of clock signals to the first inverter is stopped in response to a particular microinstruction After the supply of clock signals is stopped, the output voltage of the first inverter is clamped to a predetermined value, thus reducing the power dissipation in the dynamic CMOS circuit and also preventing the deterioration of data during the stopping of clock signalsY

ECL Compatible CMOS memory

Abstract: CMOS buffers are described which provide compatibility between a CMOS circuit and ECL circuits. The input buffer includes a comparator referenced to the V BB potential. This potential is developed on the CMOS chip with bipolar transistors integrally formed during the CMOS processing. The output buffer also utilizes a bipolar transistor and includes overshoot protection circuitry to prevent overshooting in the transition on the output line from a high potential to a low potential.

Stacked transistors CMOS (ST-MOS), an NMOS technology modified to CMOS

Abstract: This paper describes how standard NMOS technology can be modified to provide CMOS devices [1]. This is done by creating p-channel transistors in an active polysilicon layer. This stacked transistors CMOS (ST-CMOS) technology may be considered as a step towards a three-dimensional (3-D) integration, which is a possible approach for increasing the IC's packing density. All of the steps in the process are standard but one: the laser annealing of processed wafers. A crucial step in this ST-CMOS process is the laser annealing of a multilayer structure: the technique of selective annealing has been developed and optimized.

TTL Compatible CMOS input buffer

Abstract: A circuit for converting a digital signal from TTL to CMOS levels. The circuit delay is reduced by providing a transmission gate between the P and N type transistors in the first stage. This transmission gate has a high impedance during transistions and a low impedance during steady state conditions. In operation, for a rising input signal, the first stage transistors are isolated, allowing the first stage N type transistor to pull down the first stage output line without delay.

Twin-Tub CMOS II-An advanced VLSI technology

Abstract: An advanced CMOS technology has been developed for the fabrication of VLSI circuits having 2.5 µm features. The structure uses Twin-Tubs in a lightly-doped n-epitaxial layer over an n+-substrate2. Local oxidation and self-aligned chan-stops provide device isolation. The gate level has a nominal sheet resistance of 2.5Ω/□ and consists of a composite layer of TaSi 2 over n+polysilicon. The gate oxide is 350 A thick, and the electrical channel lengths for the n- and p-channel transistors are nominally 1.5 µm The threshold voltages of the n- and p-channel devices are 0.7V and -1.1V respectively. A compensating threshold-adjustment implant is used to tailor the p-channel threshold voltage. The limitations and advantages of this technique are addressed here. We present the process highlights discuss the device properties and present some of the applications of this technology.

A 64Kb CMOS RAM

Abstract: This report will cover the design of a fault-tolerant 8K×8b static RAM using a double polysilicon CMOS technology. Memory access is 70ns typically, while consuming 15mW operating power and 10μW standby power.

Measuring energy consumption in VLSI circuits: A foundation

Abstract: Energy conservation is a key question in today' s society and the proliferation of VLSI circuits encourages an energy conscious approach to their design. Although a single chip at current densities may consume less than one watt of power, assembling larger and larger systems with these chips results in significant energy costs [Me 80]. Moreover, energy consumed by a circuit is dissipated, typically by convection, as heat. The heat dissipated is proportional to the energy consumed. Increased densities in planar technologies and the possibility of 3-dimensional technologies, therefore, increase the need to reduce the amount of heal. produced. The intent of this paper is to lay the ground work for measuring the switching energy consumed in VLSI circuits. Intuitively, switching energy measures the area “used” to effect a computation. A wire or gate consumes switching energy when it changes staie from 0 to 1 or from 1 to 0. Some technologies consume more than switching energy. For example, nMOS dissipates DC power [MC 80]. CMOS, however, consumes only switching energy [MC 80]. Switching energy is thus a lower bound on total energy, and is alternately termed “energy” throughout this paper. In this paper, two energy models are developed, Model 1, the Uniswitch Model (USM), assumes that a wire or gate in an acyclic circuit can switch at most once. In particular, wire delays are neglected, the affects of different path lengths are neglected (ie. circuits are synchronous [Sa 76]), and all inputs are assumed to arrive together. Model 2, the Multiswitch Model (MSM), is more sensitive to timing issues that can cause wires and gates in an acyclic circuit to switch more than once. The rest of this paper is organized as follows. Section 2 defines the energy models. In section 3, a class of restricted acyclic circuits is defined. Lower and upper bounds for worst case energy are obtained for these circuits. An Ω(area) lower bound is obtained for acyclic monotone circuits. In section 4, average energy bounds are obtained for the restricted circuits.

Bandgap voltage reference sources in CMOS technology

Abstract: Two configurations are proposed for the implementation of bandgap reference sources in CMOS technology. The circuits presented are capable of high temperature operation, and allow a choice of the positive supply rail, the negative supply rail, or ground as the reference point.

An n-well CMOS dynamic RAM

Abstract: A new n-well CMOS dynamic RAM is proposed. Experimental results with a 4K RAM, fabricated with advanced 2-µm lithography, are presented. For the design of RAM's greater than 256K, two major problems need to be solved: the increase in substrate current, and alpha-particle-induced soft errors. The new n-well CMOS RAM technology provides a solution to these problems. Use of PMOS transistors as load elements in peripheral circuits of the n-well CMOS RAM reduces the substrate current by at least two orders of magnitude. In addition, the potential barrier between the n-type, well and the p-type substrate rejects holes generated in the substrate, resulting in the reduction of soft error rates.

Silicide contacts for cmos devices

Abstract: In the manufacture of a CMOS device, oxide is etched away from polysilicon gate-level interconnects, and from source or drain regions of either conductivity type to which the polysilicon gate-level interconnect is desired to be connected. A metal is then deposited, and silicide is formed to connect the gate-level interconnect to the respective source and drain regions. To ensure continuity of the silicide connection, the gate oxide beneath the gate level interconnect is slightly undercut by a wet etching process, additional polysilicon is deposited conformally overall, and the additional polysilicon is anisotropically etched so that it is removed from all areas except those within the undercut region beneath the gate-level interconnect thus a continuous surface of silicon, from which a continuous layer of silicide is then grown, exists between the polysilicon gate-level interconnect and the respective source and drain regions. Thus, self-aligned contacts are created, and no unwanted pn junctions are created.

Novel SOI CMOS design using ultra thin near intrinsic substrate

Abstract: A novel SOI CMOS design has been explored. It utilizes an ultra thin near intrinsic substrate wherein no channel doping is introduced during processing. The enhancement operation is realized solely by proper adjustment of work function difference through p+ poly gate for n-channel devices and n+ poly gate for p-channel devices. The absence of depletion charge in this structure is conducive to improved drive current and threshold control. The structure has been realized by implanted buried oxide SOI technology.

Injected voltage low-power CMOS for 3-valued logic

Abstract: A new family of 3-valued CMOS logic circuits that uses 2-power supplies, each below the device threshold voltage, is presented. Circuit design of basic ternary operators (inverter, NAND, NOR) is described. These basic ternary operators can be used as building blocks in 3-valued digital systems.

Microprocessor based instrument for detecting shift in basal body temperature in women

Abstract: A portable, battery powered microprocessor-based instrument for measuring basal body temperature on a daily basis and interpreting the measurement results in accordance with a cumulative sum (CUSUM) statistical test in order to recognize a shift in basal body temperature indicative of the beginning of a period of infertility. To minimize power consumption, CMOS logic devices are employed where possible, and the instrument is turned OFF except for a brief period of two or three minutes each day. The CUSUM test involves an ongoing calculation where each day's calculations depend upon results from previous days. The instrument includes an ultra low power CMOS RAM which is continuously powered and to which all necessary data is transferred under program control prior to the conclusion of each day's program execution. A predetermined range of temperature is established within which temperature readings must be in order to be accepted as valid. This predetermined range is lower during eight baseline days for which temperatures are averaged for purposes of the CUSUM test, and higher during subsequent days when an upward shift is anticipated.

An ultralow power 8Kx8-bit full CMOS RAM with a six-transistor cell

Abstract: A fully static 8K word by 8 bit CMOS RAM, with a six-transistor CMOS cell structure to achieve an extremely low standby power of less than 50 nW has been developed. A 2 /spl mu/m, double polysilicon CMOS process was utilized to realize a 19/spl times/22 /spl mu/m cell size. Redundance technology with polysilicon laser fuses was also developed for improving fabrication yield with relatively large chip size, i.e. 5.92/spl times/7.49 mm. In addition, for reducing operational power dissipation while maintaining fully static operation from outside on the chip, an internally clocked low-power circuit technology using row address transition detectors was employed, which results in only 15 mW operational power at 1 MHz by cutting off all DC current paths. The RAM offers an 80 ns address access time.

A 20K-gate CMOS gate array

Abstract: Combining an advanced 2-/spl mu/m CMOS technology with a newly developed triple-level metallization technology, a high-performance 20K-gate CMOS gate array has been developed. The advantage of triple-level metallization for area saving in a large-scale gate array was evaluated by a computer simulation. The typical gate delay is 1.5 ns with fan-out of 3, and 3-mm metal interconnect length. As a test vehicle for verifying the high-performance gate array, a 32/spl times/32-bit parallel multiplier has been successfully designed and fabricated. Cell utilization is about 65%. A typical multiplication takes 120 ns at a 5-MHz clock rate, with a power dissipation of 400 mW.