Showing papers on "Current divider published in 2005"

A broadband series power divider using zero-degree metamaterial phase-shifting lines

Abstract: A metamaterial 1:4 series power divider that provides equal power split to all four output ports over a large bandwidth is presented, which can be extended to an arbitrary number of output ports. The divider comprises four nonradiating metamaterial lines in series, incurring a zero insertion phase over a large bandwidth, while simultaneously maintaining a compact length of /spl lambda//sub 0//8. Compared to a series power divider employing conventional one-wavelength long meandered transmission lines to provide in-phase signals at the output ports, the metamaterial divider provides a 165% increase in the input return-loss bandwidth and a 155% and 154% increase in the through-power bandwidth to ports 3 and 4, respectively. In addition, the metamaterial divider is significantly more compact, occupying only 2.6% of the area that the transmission line divider occupies. The metamaterial and transmission line dividers exhibit comparable insertion losses.

Low-Voltage digitally controlled fully differential current conveyor

Abstract: Design and simulation of a digitally controlled CMOS fully differential current conveyor (DCFDCC) is presented. A novel current division network (CDN) is used to provide the digital control of the current gain between terminals X and Z of this DCFDCC. The proposed DCFDCC operates under low supply voltage of /spl plusmn/1.5 V. The realization of the DCFDCC using the new CDN is presented by two approaches. First approach has linearly proportional current gain with the digitally controlled parameter of the CDN, while the second approach exhibits current gain between terminals X and Z greater than, or equal to, one. Applications of the DCFDCC in realizing second order universal active filter and variable gain amplifier are given. PSPICE simulation confirms the performance of the proposed blocks and its applications.

Bias Current Generators with Wide Dynamic Range

Abstract: Mixed-signal or analog chips often require a wide range of biasing currents that are independent of process and supply voltage and that are proportional to absolute temperature. This paper describes CMOS circuits that we use to generate a set of fixed bias currents typically spanning six decades at room temperature down to a few times the transistor off-current. A bootstrapped current reference with a new startup and power-control mechanism generates a master current, which is successively divided by a current splitter to generate the desired reference currents. These references are nondestructively copied to form the chip's biases. Measurements of behavior, including temperature effects from 1.6 and 0.35 ? implementations, are presented and nonidealities are investigated. Temperature dependence of the transistor off-current is investigated because it determines the lower limit for generated currents. Readers are directed to a design kit that allows easy generation of the complete layout for a bias generator with a set of desired currents for scalable MOSIS CMOS processes.

A miniaturized Wilkinson power divider with CMOS active inductors

Abstract: A miniaturized Wilkinson power divider implemented in a standard 0.18-/spl mu/m CMOS process is presented in this letter. By using active inductors for the circuit implementation, a significant area reduction can be achieved due to the absence of distributed components and spiral inductors. The power divider is designed at a center frequency of 4.5GHz for equal power dividing with all ports matched to 50/spl Omega/. Drawing a dc current of 9.3mA from a 1.8-V supply voltage, the fabricated circuit exhibits an insertion loss less than 0.16dB and a return loss better than 30dB at the center frequency while maintaining good isolation between the output ports. The active area of the miniaturized Wilkinson power divider is 150/spl times/100/spl mu/m/sup 2/, which is suitable for system integration in monolithic microwave integrated circuit (MMIC) applications.

A power efficient 26-GHz 32:1 static frequency divider in 130-nm bulk CMOS

Abstract: A 32:1 static frequency divider consisting of five stages of 2:1 dividers using current mode logic (CML) was fabricated in a 130-nm bulk complementary metal-oxide semiconductor (CMOS) logic process. By optimizing transistors size, high operating speed is achieved with limited power consumption. For an input power of 0dBm, the 32:1 divider operates up to 26GHz with a 1.5-V supply voltage. The whole 32:1 chain including buffers consumes 8.97mW and the first stage consumes only 3.88mW at a 26-GHz operation. The power consumption of the first 2:1 stage is less than 15% of other bulk CMOS static frequency dividers operating at the same frequency.

A dual-frequency Wilkinson power divider: for a frequency and its first harmonic

Abstract: A Wilkinson power divider operating not only at one frequency f/sub 0/, but also at its first harmonic 2f/sub 0/ is presented. This power divider consists of two branches of impedance transformer, each of which consists of two sections of 1/6-wave transmission-line with different characteristic impedance. The two outputs are connected through a resistor, an inductor, and a capacitor. All the features of a conventional Wilkinson power divider, such as an equal power split, impedance matching at all ports, and a good isolation between the two output ports, can be fulfilled at f/sub 0/ and 2f/sub 0/, simultaneously.

Multi-frequency clock synthesizer

Abstract: A phase-locked loop (PLL) circuit includes an input for receiving a timing reference signal, a phase detector circuit coupled to receive the timing reference signal, a controllable oscillator circuit controlled according to an output of the phase detector circuit, and a feedback divider circuit having an output coupled to the phase detector and an input coupled to the controllable oscillator circuit. The phase-locked loop circuit is coupled to output one of a plurality of output signals having an arbitrary frequency relationship to each other according to a frequency selection mechanism, the frequency selection mechanism including one or more input terminals coupled to control a divide ratio of the feedback divider circuit. The frequency selection mechanism selects one of a plurality of stored values. The selected stored value controls, at least in part, a divide ratio of the feedback divider circuit, thereby providing a pin programmable device capable of selecting among output frequencies having an arbitrary relationship to each other.

Current sensing method and current sensing device, power conversion device using this current sensing device, and vehicle using this power conversion device

Abstract: A current sensing device for sensing current flowing through a MOSFET has a voltage divider circuit composed of a series circuit of a first resistor and a second resistor having different resistance temperature coefficients, with a voltage division ratio designed to change depending on temperature. The sensing device is connected between a source and a drain of said MOSFET. A sensing circuit takes out the source-to-drain voltage divided with the voltage divider to sense the current flowing through the MOSFET.

Fractional frequency divider circuit and data transmission apparatus using the same

Abstract: A fractional frequency divider circuit with a small circuit scale that outputs a clock with a duty ratio of 50%, and a data transmission apparatus comprising same. The fractional frequency divider circuit is constituted by multiple master-slave flip-flops, and comprises an integer frequency divider circuit that frequency-divides a clock signal with a frequency-division ratio of 1/N(N is an integer), and a logic circuit into which multiple signals outputted from master stages and slave stages of the master-slave flip-flops are inputted and that outputs a signal with a duty ratio of 50% obtained by frequency-dividing the clock signal with a frequency-division ratio of 2/N. The data transmission apparatus is constituted such that it is possible to switch over between a frequency-multiplied clock outputted by a PLL and a clock obtained by frequency-dividing the frequency-multiplied clock with the fractional frequency divider circuit for each channel.

A 60-GHz push-push InGaP HBT VCO with dynamic frequency divider

Abstract: We present a 60-GHz push-push voltage-controlled oscillator (VCO) with dynamic frequency divider, which is implemented in an InGaP/GaAs heterojunction bipolar transistor technology. A common-base inductive feedback topology is used in the push-push VCO, which generates a pair of 30GHz differential outputs and a single-ended 60GHz push-push output. The 30GHz differential outputs are followed by the proposed dynamic frequency divider. The proposed dynamic frequency divider incorporates active loads with inductive peaking to achieve the higher bandwidth. The maximum operating frequency of the divider was found to be much higher than f/sub T//2 of transistor. To the best of our knowledge, this is the first report demonstrating the extended bandwidth performance of the dynamic frequency divider with active loads and inductive peaking.

A 15-GHz broad-band /spl divide/2 frequency divider in 0.13-/spl mu/m CMOS for quadrature generation

Abstract: This letter presents a 0.13-/spl mu/m CMOS frequency divider realized with an injection-locking ring oscillator. This topology can achieve a larger input frequency range and better phase accuracy with respect to injection-locking LC oscillators, because of the smoother slope of the loop gain phase-frequency plot. Post layout simulations show that the circuit is able to divide an input signal spanning from 7 to 19GHz, although the available tuning range of the signal source limited the experimental verification to the interval 11-15GHz, featuring a 31% locking range. The divider dissipates 3mA from a 1.2-V power supply.

High frequency divider circuits and methods

Abstract: Embodiments of the present invention include circuits and methods for dividing high frequency signals. In one embodiment the present invention includes a divider circuit comprising a differential circuit having first and second inputs to receive a first differential signal, a first frequency control input and first and second differential outputs, wherein the differential circuit has a first bias current. The divider circuit further includes a cross-coupled circuit having outputs coupled to the differential circuit outputs and a second frequency control input, wherein the cross-coupled circuit has a second bias current. Embodiments of the present invention may include circuits for controlling the relationship between bias currents and circuit parameters that vary with process or temperature or both.

Integrated clock generator with programmable spread spectrum using standard PLL circuitry

Abstract: An apparatus comprising a phase lock loop circuit and a control circuit. The phase lock loop circuit may be configured to generate an output signal having a first frequency in response to (i) an input signal having a second frequency, (ii) a first divider value and (iii) a second divider value. The second divider value may control spread spectrum modulation of the phase lock loop circuit. The control circuit may be configured to generate the second divider value in response to (i) the output signal and (ii) a programmable control signal.

Compact EBG in-phase hybrid-ring equal power divider

Abstract: A novel electromagnetic-bandgap (EBG) in-phase hybrid-ring equal power divider is described. Coupled with the closed-form analytical expressions for the EBG structure, a systematic technique of design is presented for the first time. Compared to the conventional hybrid-ring equal power divider, based on the 15-dB return-loss criteria, an increase in both the input and output impedance bandwidth of approximately 10% from a starting frequency of 2.5 GHz, and a phase error of 0.006/spl deg/ within the passband have been achieved for the proposed structure. The proposed in-phase hybrid-ring equal power divider, besides providing a much broader bandwidth and occupying a smaller estate area, also possesses good harmonic suppression characteristic.

Apparatus and method for in-process high power variable power division

Abstract: A power divider for a waveguide between a single electromagnetic microwave generator input and two output ports, the divider including two tuner networks, each comprising a moveable capacitive probe with a pair of fixed flanking inductive posts.

A dual-mode truly modular programmable fractional divider based on a 1/1.5 divider cell

Abstract: A divide-by-1/1.5 divider cell using a dual edge-trigger technique is proposed. Based on this divider cell, a dual-mode programmable divide-by-X circuit is demonstrated in 0.18-/spl mu/m CMOS technology, where X=P or P.5 in one mode and 2P or 2P+1 in the other mode with P=128-255. When operated in the divide-by-2P/2P+1 mode, this circuit outputs a signal with 50% duty cycle. Theoretically, P can be any arbitrary and programmable integer.

Self-calibrating device for measuring voltage and corresponding method

Abstract: A device for measuring a battery voltage is a self-calibrating device. The battery voltage is connected to a voltage divider formed of series-connected resistors, or components that are subject to a voltage drop. For the purposes of calibration the voltage divider is separated from the battery voltage and a reference current or reference voltage source is connected to the voltage divider in its place. The voltages dropping across the voltage divider are measured and an actual resistance ratio of the resistors of the voltage divider is calculated, based on the measured voltages. The voltage divider is then re-connected to the battery voltage that is to be measured and a battery voltage is determined with the aid of the voltage divider, taking into account the calculated resistance ratio.

Fully integrated CMOS fractional-N frequency divider for wide-band mobile applications with spurs reduction

Abstract: A spurs reduction fractional-N frequency divider with a frequency range which is 3.5 times larger than that of a conventional fractional-N divider is presented in this paper. A 1.2-GHz quadrature voltage-controlled oscillator (VCO) is designed as the input source of the frequency divider. The circuit was fabricated using the 0.25-/spl mu/m CMOS technology. The power consumption of the frequency divider and the quadrature VCO are 3 and 6 mW, respectively, at a 2-V supply.

Tunable high-speed frequency divider

Abstract: A locking range of a current mode logic (CML) frequency divider circuit is tunable by dynamically adjusting a tail current of the frequency divider circuit according to a control signal. The control signal may be based on at least one control signal coupled to tune a controllable oscillator. The control signal may be based on a frequency of an output of a voltage controlled oscillator coupled to the frequency divider. The control signal may be based on the voltage swing of an output of a voltage controlled oscillator coupled to the frequency divider. The control signal may be based on an output of the frequency divider circuit.

Enhanced fault protection in electricity meter

Abstract: An arrangement for obtaining measurable voltage signals in a utility meter includes a first connection to a phase of a power line, a second connection to a reference of a power line, a voltage divider circuit, and a series inductor. The voltage divider circuit is disposed on a circuit board and is coupled between a first node and the second connection. The voltage divider circuit has an output configured to provide measurable voltage signals to a circuit operable to generate voltage measurement information. The series inductor is disposed apart from the circuit board and is configured for current limiting. The series impedance element is coupled between the first connection and the first node.

Driver circuit for light emitting element

Abstract: Disclosed is a display driver that includes a first current driver circuit, a second current driver circuit and a reference current source circuit. The first current driver circuit, which has plural current sources the output current values of which are determined based on a reference current, and switch circuits for on/off controlling the current path between the plural current sources and the current output terminal based on video signal composed of plural bits. The first current driver circuit outputs a first output current conforming to the video signal. The second current driver circuit outputs the second output current conforming to the video signal, while the reference current source circuit variably controls the reference current based on the value of the video signal. A current that is the result of combining the first and second output currents from the first and second current driver circuits is output as an output current. An amount of change in the output current that corresponds to a change of one LSB of the video signal, is varied in accordance with the value of the video signal, the gamma characteristic is approximated by piece-wise linear approximation and the overall luminance of the display pane is variably controlled based on a control signal from a panel luminance adjustment circuit.

Single-pin tracking/soft-start function with timer control

Abstract: A voltage regulator includes a voltage divider connected between a soft-start pin and the voltage regulator's error amplifier. The voltage divider has the same divider ratio as that of the voltage regulator's feedback voltage divider, which is used to divide the regulated output voltage fed back to the error amplifier. To facilitate soft-start operations, an external, user-supplied capacitor is connected to the soft-start pin. To facilitate voltage tracking operations, a predetermined master supply voltage is applied to the soft-start pin.

Diagnosable switch arrangement has potential divider and state of switch arrangement can be determined by measuring voltage between potential divider node and earth potential of potential divider

Abstract: The switch arrangement has a physical switch (10) with open and closed states, at least one first switch resistance in series with the physical switch, at least one second switch resistance in parallel with the first switch resistance and the physical switch, a first switch contact (12) connected to the node (5) of a potential divider circuit (15) and a second switch contact (13) connected to the earth potential (14) of the potential divider circuit. The state of the switch arrangement can be determined by measuring the voltage between the potential divider node and the earth potential.

Transceiver circuit and method for providing local oscillator signals in a transceiver circuit

Abstract: A transceiver circuit includes a transmission path and also at least two reception paths, which in each case contain a frequency conversion device with a local oscillator input. A first, a second and a third oscillator circuit, and also a programmable frequency divider circuit are furthermore provided. The outputs of the oscillator circuits are connected to a respective input of the programmable frequency divider circuit. The frequency divider circuit contains three outputs connected in each case to a local oscillator input of the transmission path and the two transmission paths. According to one example of the invention, the frequency divider circuit is designed for frequency division of a signal present at an input and for outputting the frequency-divided signal to one of the three outputs. With the programmable frequency divider circuit, signals at the three inputs of the frequency divider circuit can thus be divided arbitrarily in terms of their frequency and be output at the outputs in a manner dependent on the desired operating mode of the transceiver circuit.

Current sense shunt resistor circuit

Abstract: Current through a wire is sensed with a shunt resistor and a sense resistor in a current divider circuit. The values of the shunt resistor and sense resistor are related to provide a specified gain ratio to increase a dynamic range of current measurement. The sense resistor is a trimmable resistor, the configuration of which can be discerned from a look-up table based on a level of precision needed for current measurement. The two resistors can also be related by thermal coefficients to improve linearity of current measurements.

Digitally controlled fully differential current conveyor: CMOS realization and applications

Abstract: Design and simulation of a digitally controlled CMOS fully differential current conveyor (DCFDCC) is presented. A novel current division network (CDN) is used to provide the digital control of the current gain between terminals X and Z of this DCFDCC. The proposed DCFDCC operates under low supply voltage of /spl plusmn/1.5V. Application of the DCFDCC in realizing second order universal active filter is also given. PSPICE simulation confirms the performance of the proposed blocks and its application.

Variable attenuation network

Abstract: A variable attenuation network of an input voltage on an input node produces an attenuated voltage on an output node of the network, and includes a voltage divider with multiple-taps that are selectable for producing the attenuated voltage from a voltage applied on the terminals of the voltage divider. The attenuation network produces an output voltage with an attenuation ratio that is determined with at least twice the resolution of the voltage divider, because it includes at least one resistor that may be shorted by a low impedance by-pass line controlled by a switch and alternatively connected between the selected intermediate tap or any one of the two terminals of the voltage divider and the output node of the variable attenuation network, the input node of the attenuation network or a common ground node, respectively. By using more than one shortable resistor, multiple levels of resolution may be obtained.

Power divider and combiner in communication system

Abstract: Disclosed is a high frequency omni-directional 2-way power divider which includes one input terminal and two output terminals so that a signal inputted through the input terminal is uniformly distributed to the two output terminals. The high frequency omni-directional 2-way power divider includes: a first Wilkinson regular divider including one input terminal and first and second output terminals; a second Wilkinson regular divider including one input terminal and third and fourth output terminals, the third output terminal being connected to the first output terminal of the first Wilkinson regular divider; and a third Wilkinson regular divider including one input terminal and fifth and sixth output terminals, the fifth output terminal being connected to the second output terminal of the second Wilkinson regular divider and the sixth output terminal being connected to the fourth output terminal of the second Wilkinson regular divider, wherein, when one of the three input terminals contained in the first to the third Wilkinson regular divider is used as the input terminal of the 2-way power divider, other two input terminals are used as output terminals, to which power is uniformly distributed.

Method to improve high frequency divider bandwidth coverage

Abstract: A divider for a local oscillator (LO) generator system of a phase locked loop (PLL) in a transceiver chip. The divider includes at least one divider unit. Each divider unit includes a frequency divider unit for receiving an input signal having an input frequency and for outputting an output signal having an output frequency which is approximately one half of the input frequency. Each divider unit also includes a resistor bank coupled between a voltage source and the frequency divider unit, and a current stirring unit for supplying current to the frequency divider unit. The resistance of the resistor bank and a magnitude of the current supplied by the current stirring unit are variable depending on the input frequency.