Showing papers on "Depletion region published in 1987"

High-temperature cubic boron nitride p-N junction diode made at high pressure.

Abstract: A p-n junction diode of cubic boron nitride was made by growing an n-type crystal epitaxially on a p-type seed crystal at a pressure of 55 kilobars and a temperature of about 1700°C. A temperature-difference solvent method was used for the crystal growth, and beryllium and silicon were doped as acceptors and donors, respectively. Formation of the p-n junction was clearly confirmed at 1 bar by rectification characteristics and by existence of a space charge layer of the junction as observed by electron beam induced current measurement. This diode operated at 530°C.

Contactless technique for semicondutor wafer testing

Abstract: A contactless technique for semiconductor wafer testing comprising: depositing charges on the top surface of an insulator layer over the wafer to create an inverted surface with a depletion region and thereby a field-induced junction therebelow in the wafer, with an accumulated guard ring on the semiconductor surface therearound The technique further includes the step of changing the depth to which the depletion region extends below the inverted semiconductor wafer surface to create a surface potential transient, and the step of measuring a parameter of the resultant surface potential transient This technique may be utilized to make time retention and epi doping concentration measurements It is especially advantageous for reducing the effects of surface leakage on these measurements In a preferred embodiment, corona discharges are used to effect the charge deposition configuration Either corona discharge or photon injection are used to change the depletion region depth

Semiconductor nonvolatile memory

Abstract: A floating gate type semiconductor non-volatile memory injects carriers from a carrier supply region to a floating gate by a phenomenon called "punch-through" injection in which a space charge region is formed in a semiconductor substrate between the carrier supply region and a carrier injection region so as to accelerate the carriers and inject them into the floating gate without forwardly biasing the carrier injection region or the substrate.

Blocked impurity band detectors—an analytical model: Figures of merit

Abstract: We are presenting an analytic model for the figures of merit of a novel extrinsic infrared quantum detector—the blocked impurity band (BIB) detector. The detector consists of top and bottom contacts, a heavily doped active layer, and a nearly intrinsic layer, called the blocking layer, to stop the motion of hopping carriers in the impurity band. The responsivity, gain, excess noise factor, and detectivity of the BIB detector are calculated as functions of the device dimensions, doping concentrations, and the applied reverse bias, which controls the electric field in the depletion region, devoid of hopping carriers, of the device underneath the blocking layer. Central to our model is the inclusion of impact ionization of carriers in the calculation of the detector response and of the associated noise. For practical detector dimensions and doping concentrations, and at 2‐V reverse bias, we calculate the responsivity to be on the order of 2 A/W, and detectivities, with 1012 photons/cm2 s background photon fl...

Influence of substrate freeze-out on the characteristics of MOS transistors at very low temperatures

Abstract: The low temperatures current-voltage characteristics of N-channel MOS transistors have been analysed. An excess drain current is observed for intermediate values of drain voltage. This anomalous drain current is explained in terms of substrate freeze-out, since at very low temperatures the MOS structure has a type of floating substrate potential within the depletion region. Due to the increase of the majority carrier current, flowing through the substrate to the source at increasing drain voltage, this substrate potential increases and causes a change of threshold voltage. This change is observed in the current-drain voltage characteristics of the MOSFET. Various experiments, such as measurements of substrate current, effects of temperature, gate and substrate voltages, support this interpretation. MOS transistors with various geometries and various dopings are analysed.

Leakage current characteristics of offset-gate-structure polycrystalline-Silicon MOSFET's

Abstract: Leakage current characteristics of offset-gate-structure polycrystalline-silicon (poly-Si) MOSFET's are studied as a function of dopant concentration N off in offset-gate regions. Leakage current markedly decreases from 1 × 10-9to 2 × 10-11A at V D = 10 V as N off is varied from 1 × 1018to 1 × 1017cm-3. A maximum ON/OFF current ratio of 108is obtained at 1 × 1017cm-3. Calculations based on a quasi-two-dimensional model indicate that the reduction of leakage current is attributable to a decrease of the maximum lateral electric field strength in the drain depletion region. An analysis of the leakage current characteristics in terms of carrier emission from grain-boundary traps implies that thermonic emission accompanied by thermally assisted tunneling could be the dominant mechanism in determining leakage current.

MOS field effect transistor and method of manufacturing the same

Abstract: A MOS field effect transistor comprising a semiconductor substrate (1) and an epitaxial growth layer (2) provided on the substrate, the impurity concentration of the epitaxial growth layer being lower than that of the substrate, and the thickness of the epitaxial growth layer being the same as or less than the thickness of a depletion region as a channel region. The invention also provides methods of making such transistors.

Analytic Modeling Of Charge Diffusion In Charge-Coupled-Device Imagers

Abstract: Depending on the device structure and hence the electric field present within a CCD, there is often a considerable time for charge clouds generated within the silicon to diffuse and spread outward before being collected at the buried channel. This charge spreading has an important effect on the spatial and energy resolution of CCDs used for soft x-ray, optical, and high energy particle imaging. Further theory on this is presented with regard to the performance of CCDs currently under development, to broaden their spectral response while minimizing the thickness of the field-free region below the depletion layer. It is shown that the charge cloud profiles resulting from field-free diffusion have broad wings that can lead to significant charge splitting between adjacent pixels, even for field-free region thicknesses ~1 um. Formulas are also presented for diffusion in the field region and the substrate.

Semiconductor memory device

Abstract: PURPOSE:To improve the efficiency and the accuracy of information writing by deeply inverting the separating region of a source region and a floating gate at writing time in an EPROM, thereby preventing between the source and the drain from punching through. CONSTITUTION:An EPROM cell has an N type drain region 4 and an N type source region 5 in an element forming region separated and presented at a P type silicon substrate 1 by a field SiO2 film 2 and a P-type channel stopper 14. A floating gate 7 made of polycrystalline silicon layer is arranged, and a control gate 9 made of polycrystalline silicon layer is extended and disposed on the region 5 and the separating portion OFS. A deep inverted layer INV is formed on the substrate of the separating portion OFS by a selective voltage applied to the gate 9 at writing time, the layer INV suppresses the extension of a depletion layer DEP, thereby effectively writing without punch- through between the source and the drain.

Measurement of SEU Thresholds and Cross Sections at Fixed Incidence Angles

Abstract: Current SEU testing and analysis techniques have as basic assumptions that the charge deposited at a junction depends linearly on the linear energy transfer (LET) of the ion and the pathlength of the ion through an imagined parallelepiped that represents the depletion region. This study tests these assumptions for two bipolar parts, AMD 27LSOO and Fairchild 93L422, by irradiating at fixed angles while varying the LET of two ion species. It was found that the 27LSOO shows a pronounced ion species dependence, and may show a deviation of deposited charge from the usual inverse-cosine times a fixed depletion depth, while the 93L422 exhibited the expected inverse-cosine dependence and no ion species dependence.

Two‐dimensional electron gas structures with mobilities in excess of 3×106 cm2 V−1 s−1

Abstract: We have demonstrated that the mobility of two‐dimensional electron gas (2DEG) structures shows a gradual improvement with the number of uninterrupted growth runs in the molecular‐beam‐epitaxy system. Some, but not all, of this improvement can be attributed to the cleanup of the GaAs layers in the structure, and we suggest that there is a corresponding cleanup of the (Al,Ga)As which is also influencing the mobility. Once the system has passed the cleanup phase, a systematic trend of carrier density and mobility with undoped spacer thickness was observed, with a peak mobility at 4 K of 2.12×106 cm2 V−1 s−1 for a sheet carrier density of 2×10−11 cm−2 occurring at a spacer thickness of 800 A. A further increase in mobility was achieved by using a thicker region of doped (Al,Ga)As, thereby moving the ionized centers in the surface depletion layer further away from the 2DEG. This has enabled us to produce a sample with mobility at 4 K of 3.1×106 cm2 V−1 s−1 (at a sheet charge of 3.1×1011 cm−2)—the first time su...

Laser-recrystallized polycrystalline-silicon thin-film transistors with low leakage current and high switching ratio

Abstract: Laser-recrystallized polycrystalline-silicon thin-film transistors (poly-Si TFT's) with offset-gate structures have been fabricated on quartz substrates. Offset-gate structures make it possible to reduce leakage currents to as low as 5 × 10-14A/µm at V D = 10 V, more than two orders of magnitude lower than that in conventional-structure poly-Si TFT's. Optimization of the dopant concentration in offset-gate regions minimizes degradation of drive current, enabling high switching ratios exceeding 108. Calculations based on the quasi-two-dimensional model indicate that the reduction in leakage current is due to a decrease in lateral electric field strength in the drain depletion region.

Spectroscopy of delayed electronic transitions in GaAs Schottky diodes

Abstract: Dielectric spectroscopy of semiconductors (DSS) reveals the frequency spectra of delayed electronic transitions in semi-insulating systems and it may be used to study the trapping/de-trapping processes in the space charge regions of Schottky diodes and at the metal-semiconductor interfaces. The authors report measurements for two types of diodes with different bulk doping, in the frequency range 0.01 Hz to 10 kHz, with the temperature and bias as variable parameters. The trapping processes in the space charge region are shown to have non-exponential time dependence, and the interfacial processes give strong deviations from the classically expected behaviour at very low frequencies and high temperatures, with a strong dependence on external bias. Certain phenomena appear to point to many-body interactions having a role in determining the rate processes in these Schottky diodes.

Nondestructive readout of a latent electrostatic image formed on an insulating material

Abstract: A method and apparatus are described for the nondestructive readout of a latent electrostatic image formed on a sheet or layer of insulating material. A sheet or layer of semiconductor material is disposed in relatively close proximity to the insulating material. A latent electrostatic image formed on the insulating material (by any known means) causes a surface depletion layer to be produced by induction at the surface of the semiconductor material. The location and distribution of the accumulated charges on the semiconductor material are read out as analog electrical signals corresponding to the AC surface photovoltage induced on the semiconductor material as the semiconductor material is scanned with a low intensity modulated light beam of appropriate wavelength, the magnitude of the analog signals depending on the local charge density. The analog electrical signals so obtained are then digitized, processed and stored and/or displayed.

On the punchthrough characteristics of advanced self-aligned bipolar transistors

Abstract: This paper presents a detailed two-dimensional numerical simulation study on the punchthrough characteristics of advanced self-aligned bipolar transistors utilizing a sidewall spacer technology. Particular emphasis is placed on the effect of the sidewall spacer thickness. Perimeter punchthrough due to insufficient extrinsic-intrinsic base overlap is shown to be a major concern. The tradeoff between the punchthrough current and the maximum surface electric field in the depletion region of the extrinsic base-emitter junction, which relates closely to the perimeter tunneling current, is discussed.

Bipolar inversion channel device

Abstract: A new solid state field effect bipolar device provides for high current gain and low input capacitance, while avoiding the "punch-through" effects that limit the downward scaling of conventional bipolar and field effect devices. The device typically comprises a metallic (e.g. a metal or silicide) emitter, which makes ohmic contact to a semi-insulator; a channel terminal which contacts an inversion layer formed at the interface between the semi-insulator and a semiconductor depletion region; and a collector, which is the semiconductor bulk. The novel device controls the flow of majority carriers from the emitter into the collector by the biasing action of charge in the inversion channel. The technique can be utilized in making a transistor, photodetector, thyristor, controlled optical emitter, and other devices.

Application of deep level transient spectroscopy to metal‐oxide‐semiconductor relaxation transients

Abstract: A method for determining minority carrier generation lifetimes and hold times in metal‐oxide‐semiconductor devices is presented. The technique overcomes some of the uncertainties inherent in the commonly used Zerbst lifetime measurement and can be used on very small devices. In the method a deep level transient spectroscopy system is used to separate generation currents of different activation energies, and to provide values for these energies, so indicating the source of the generation at a particular temperature. In the range where generation in the depletion region is dominant, the minority‐carrier generation lifetime can be derived. In all cases the data can be directly related to the ‘‘hold’’ time of a metal‐oxide‐semiconductor capacitor.

Charge transfer kinetics at semiconductor electrodes

Abstract: In the present paper various factors influencing the kinetics of charge transfer processes at semiconductor electrodes are described. It is shown that the interfacial currents can be determined by the interfacial kinetics as well as by the transport of electrons and holes through the space charge layer. In the case of minority carriers created by light excitation the corresponding photocurrent-potential dependence is frequently influenced by minority carrier trapping at the interface. In addition the influence of surface chemistry such as e.g. oxide formation is demonstrated for some photoelectrochemical reactions. Various models are presented and discussed in detail.

Method for the examination of electrically active impurities of semiconductor materials or structures and measuring arrangement for carrying out the method

Abstract: A method for the examination of electrically active impurities of semiconductor materials or semiconductor structures is disclosed. The method comprises the steps of providing a junction in a sample taken from the semiconductor to be tested, inserting the sample in a microwave field, providing a space charge layer in the junction by applying a reverse bias thereto, filling the electrically active defects of the space charge layer, and examining the thermal emission process proceeding to reach a thermal equilibrium state that occurs following the filling step by measuring the change of the microwave field that takes place due to changes in microwave absorption in the sample during the thermal emission process. The microwave field should be present at least during the examination of the transient microwave absorption. In a measuring arrangement for carrying out the method a sample (24) of the semiconductor comprises a junction, the sample is provided with a pair of electrical contacts, and the measuring arrangement comprises a biasing means (26) coupled to the contacts for reverse biasing the junction to provide a space charge layer therein, a means (26) for filling the electrically active defects in the layer during a predetermined period or periods, and transient detecting means (27) for detecting transient changes in the junction after termination of said periods. The arrangement further comprises a microwave generator (21), a microwave means (23) coupled to the generator which defines a microwave field, and the sample is arranged in the field of the microwave means with a contact coupled to ground. The transient detecting means (27) is a microwave detector arranged to detect transient changes in microwave absorption due to the changes in the junction.

Depletion corrections in variable temperature Hall measurements

Abstract: The decrease in the measured Hall free‐electron concentration with decreasing temperature near 300 K is often observed for thin high‐purity GaAs layers. This has previously been interpreted as electron freezeout on deep donor sites. However, it can be quantitatively described by the decrease in carrier concentration per unit area associated with increasing surface and interface depletion region thicknesses. It is shown that when these depletion regions are included in the analysis of the Hall‐effect data, the measured free‐electron freezeout behavior can be accurately described by a simple shallow donor. If necessary, a deep donor may be included in the modeling. The results agree with the observed temperature variation of the capacitance‐voltage (C‐V) profiling data.

AlGaAs/GaAs heterojunction bipolar transistors with small size fabricated by a multiple self-alignment process using one mask

Abstract: A multiple self-alignment process for HBT's using one mask is developed to form emitters, emitter contacts, emitter contact leads, buried small collectors, base contacts, and base contact leads. This process makes it possible to produce HBT's of very small size and to reduce parasitic elements. An AlGaAs/GaAs HBT fabricated by the process, with an emitter 1 × 20/µm2in size and a buried collector by O+implantation gives a good performance of f t = 54 GHz and f max = 42 GHz. The performance may be explained by the reduction of parasitic elements, base transit time, and collector depletion layer transit time.

Method for fabricating edge channel FET

Abstract: Edge channel FET structural geometry and processing is disclosed. A plurality of mesa stacked horizontal layers are provided including source and drain semiconductor layers (74, 76) separated by an insulator layer (75) and having exposed edges (78, 80) at a generally vertical side (83) of the mesa. A generally vertical semiconductor layer (84) extends along the side of the mesa over the exposed source and drain layer edges and forms a channel (93). A gate layer (91, 92) on the channel controls depletion region spreading in the channel layer to control conduction therethrough between the source and drain layers. Channel length is extremely small, as low as 0.1 micron. Ohmic contacts (87, 90) to the source and drain layers are defined several microns away from the conducting channel, resulting in considerable reduction in fabrication complexity, as well as improved reliability. Fabrication and alignment of the gate to the active channel layer is simplified.

The contribution of bulk states to the ac conductance of metal‐insulator‐semiconductor diodes

Abstract: Measurements of the density of interface states in metal‐insulator‐semiconductor diodes by conductance techniques have revealed two resonances in the equivalent parallel conductance. Interface states are responsible for one, but the other is due to bulk states in the silicon crossing the Fermi energy in the depletion region. This latter contribution is found to resonate at a fixed frequency independent of the bias applied to the diode, unlike the interface state response which varies in the normal way. From the maximum in the equivalent parallel conductance we have calculated the density of bulk states to be 1014 cm−3 and identified sodium as the likely impurity responsible.

Photoelectric converting device

Abstract: A photoelectric converting device comprises a first semiconductor area of a first conductivity type, a second semiconductor area of a second conductivity type, and a third semiconductor area of the first conductivity type. A charge is photoelectrically excited by light incident on the second semiconductor area, and is derived from the first semiconductor area after amplification. A fourth semiconductor area of the first conductivity type is formed in contact with the second semiconductor area and so positioned corresponding to the third semiconductor area. During operation of the device, a depletion layer extending from the interface between the third and fourth semiconductor areas reaches a depletion layer extending from the interface of the third and second semiconductor areas.

Semiconductor device having floating semiconductor zones

Abstract: A semiconductor device has a surface zone which forms a planar pn junction with the surrounding substrate, this pn junction being biased in operation in the reverse direction. In order to increase the breakdown voltage, one or more floating zones are located beside the pn junction within the range of the depletion zone, which also form planar pn junctions with the substrate. According to the invention, the floating zones have an overall doping of at least 3·10 11 and at most 5·10 12 atoms/cm 2 , as a result of which they are substantially depleted at a high reverse voltage.

Reverse Current Characteristics of Hydrogenated Amorphous Silicon-Crystalline Silicon Heterojunctions

Abstract: The electrical properties of heterojunctions of p-type a-Si:H and n-type c-Si have been investigated by measuring I–V and C–V characteristics. The C–V characteristics revealed that there was something (what is called interface defect states) to obstruct the spread of the depletion layer in c-Si at the interface of a-Si:H and c-Si. The I–V characteristics showed that these interface defect states assisted the generation of a reverse current. The calculation suggested that only the interface defect states near the midgap influenced the reverse current. Consequently, to realize a low dark current applicable to imaging devices, it was necessary to decrease the number of interface defect states.