Showing papers on "Digital electronics published in 1987"

COSMOS: a compiled simulator for MOS circuits

Abstract: The COSMOS simulator provides fast and accurate switch-level modeling of MOS digital circuits. It attains high performance by preprocessing the transistor network into a functionally equivalent Boolean representation. This description, produced by the symbolic analyzer ANAMOS, captures all aspects of switch-level networks including bidirectional transistors, stored charge, different signal strengths, and indeterminate (X) logic values. The LGCC program translates the Boolean representation into a set of machine language evaluation procedures and initialized data structures. These procedures and data structures are compiled along with code implementing the simulation kernel and user interface to produce the simulation program. The simulation program runs an order of magnitude faster than our previous simulator MOSSIM II.

Interconnect testing with boundary scan

Abstract: Boundary scan is a structured design technique which can be used to simplify the testing of digital circuits, boards, and systems. With boundary scan, test patterns can be generated which provide 100% stuck-at and bridging fault coverage of board interconnections. The paper describes the advantages and disadvantages of boundary scan along with the application and implementation of boundary scan circuitry. Algorithms for generating interconnect test patterns for stuck-at and bridging fault coverage are also presented

Boolean Analysis of MOS Circuits

Abstract: The switch-level model represents a digital metal-oxide semiconductor (MOS) circuit as a network of charge storage nodes connected by resistive transistor switches. The functionality of such a network can be expressed as a series of systems of Boolean equations. Solving these equations symbolically yields a set of Boolean formulas that describe the mapping from input and current state to the new network states. This analysis supports the same class of networks as the switch-level simulator MOSSIM II and provides the same functionality, including the handling of bidirectional effects and indeterminate (X) logic values. In the worst case, the analysis of an n-node network can yield a set of formulas containing a total of O(n /sup 3/) operations. However, all but a limited set of dense, pass-transistor networks give formulas with O(n) total operations. The analysis can serve as the basis of efficient programs for a variety of logic design tasks, including logic simulation (on both conventional and special-purpose computers), fault simulation, test generation, and symbolic verification.

Ultimate performance of the RSFQ logic circuits

Abstract: A new family of dc-powered Josephson junction digital devices, the Rapid Single Flux Quantum (RSFQ) logic, is described. The devices use overdamped Josephson junctions and two-junction interferometers to store, pass and process the digital information presented in form of single flux quanta. We have carried out extensive numerical simulation of the dynamics of the RSFQ logic gates and of some more complex circuits including serial full adder and reversible shift register, within the standard microscopic-theory ("Werthamer") description of Josephson junctions. The minimum clock cycles of the basic RSFQ circuits turn out to be as small as 2.5 ps. The most promising ways to use the RSFQ logic circuits at the present stage of development of the Josephson junction digital technology are discussed.

Timing Analysis and Performance Improvement of MOS VLSI Designs

Abstract: TV is a MOS VLSI switch-level timing verifier It has built-in direction-finding through pass transistors to minimize the number of false paths found, and has knowledge of clocking disciplines to increase the usefulness of timing analysis for chips with several clock phases TV can find several distinct critical paths at once by using a modified breadth-first search, so that the number of runs of the timing verifier is reduced over systems providing single or multiple equivalent paths It can analyze circuits with 40000 transistors in under 30 min of VAX 11/780 CPU time The IA is TV's novel interactive timing advisor that provides incremental timing analysis The IA can compute the effects of small design changes in circuits with 100 000 transistors using only seconds of CPU time The IA Autopilot can propose and evaluate its own design changes

Analog transducer circuit with digital control

Abstract: A two wire transmitter (10) controls loop current as a function of a sensed parameter such as pressure or temperature using analog sensing and signal processing circuitry. Corrections, such as for zero, span, and linearity are provided in the form of analog correction signals by a digital circuit which includes a nonvolatile memory (36), a microcomputer (32), and a digitial-to-analog (D/A) converter (26). The microprocessor (32) controls the D/A converter (26) as a function of stored digital correction values to produce the analog correction signals used by the analog signal processing circuitry to control the magnitude of the loop current flowing through the two wire transmitter (10).

Designing CMOS Circuits for Switch-Level Testability

Abstract: Conventional testing techniques often fail to be effective for CMOS combinational circuits, since most of their switch-level faults cannot be detected by stuck-at-fault testing. The alternative is to design for testability. The design techniques presented here for fully testable CMOS combinational circuits use a three-pattern test scheme to detect both stuck-open and stuck-on switch-level faults. The circuit is implemented with specially designed gates that have no undetectable stuck-on faults. An inverting buffer is inserted between logic gates, and two FETs are added to each logic gate to make it testable for stuck-on faults.

Performance-Oriented Synthesis of Large-Scale Domino CMOS Circuits

Abstract: The quality of the design of large-scale integrated circuits is determined by such figures of merit as silicon area, power consumption, and switching-time performance. We address here the problem of the automatic synthesis of digital circuits with the goal of achieving high-performance designs. We assume we are given an intermediate circuit representation that optimizes area and/or power. We use timing optimization techniques to improve the circuit performance, possibly at the expense of the other figures of merit. We consider general classes of digital circuits, with a given partition into registers, combinational blocks, and I/O ports. Circuit performance is related to the worst-case propagation delay of signals between two register boundaries. In this context, circuit performance optimization is equivalent to minimizing the critical path delay through the combinational circuits. We assume a multiple-level implementation of the combinational logic, by means of an interconnection of logic gates implementing arbitrary multiple-input, single-output logic functions. We consider dynamic CMOS implementation of the logic gates, operating in the domino mode. We present a global approach to timing performance optimization, which involves operations at the logic, topological, and physical level of abstraction of the circuit. In particular, at the logic level, we look for optimal structures of multiple-level combinational networks. At the topological level, we search for the optimal positions of gates or groups of gates. At the physical design level, we optimize MOS device sizes. The algorithms are described, together with their implementation and the interface to the Yorktown Silicon Compiler system, which is an automated synthesis system described in [7]. The results of applying timing-performance optimization to a 32-bit microprocessor design are reported.

Analysis and modeling of multilevel parallel and crossing interconnection lines

Abstract: Analytical and numerical techniques to study the pulse propagation characteristics such as delay, distortion, and crosstalk in multilevel interconnections associated with high-speed digital IC's including VLSI chips are presented. The parallel and crossing interconnections at various levels are modeled as lossy coupled lumped distributed parameter systems, which are analyzed for their time domain characteristics. The characterizing electrical parameters of the structures are computed by utilizing the network analog method that has been formulated to solve for the lossy line constants and parasitic coupling associated with a three-dimensional multiconductor system in a layered lossy medium. It is shown that the time domain response of the multiport structures can be computed by using standard CAD programs such as SPICE by utilizing compatible circuit models developed from the solution of such systems. Examples of the step and pulse response of typical systems are included to demonstrate the versatility, usefulness, and accuracy of the techniques presented in the paper.

CMOS differential pass-transistor logic design

Abstract: This logic technique offers greater area efficiency, higher speeds of operation, and simpler design algorithms than conventional CMOS pass-transistor logic. Experimental results and the automated techniques used in implementing efficient pass-transistor layouts are presented. The application of CMOS differential pass-transistor logic design in custom applications is also discussed.

Method for generating efficient testsets for a class of digital circuits

Abstract: A digital logic circuit is broken into functional blocks, each having a path from its output port to a chip level output port. No two input patterns to that path produce the same output pattern on that path and for every path input pattern there is a one-to-one relation with the path output pattern regardless of the transformation of that pattern by the path. All other path inputs are independent of the path test patterns such that a block test output pattern applied to that path is not fault affected by those other path inputs. The circuit is partitioned into testable blocks whose outputs are coupled by such paths to observable chip output ports. The chip level tests for all block test patterns are screened to eliminate redundant block tests to produce a practical set of test vectors.

An Introduction to Switch-Level Modeling

Abstract: Switch-level modeling is a recently developed design and analysis methodology for MOS VLSI circuits. At the switch level, important features of MOS circuits can be directly modeled using a moderate number of discrete parameters, including switch states, resistance, capacitance, and bidirectional signals. Switch-level models, provide more accurate behavioral and structural information than gate-level logical models, while avoiding the high computational cost associated with analog electrical models.

Logic Verification Algorithms and their Parallel Implementation

Abstract: LOVER incorporates a novel approach to combinational logic verification and obtains good results when compared to existing techniques. In this paper we describe a new verification algorithm, LOVER-PODEM, whose enumeration phase is based on PODEM. A variant of LOVER-PODEM, called PLOVER, is presented. We have developed, for the first time, parallel logic verification schemes. Issues in efficiently parallelizing both general and specific LOVER-based approaches to logic verification over a large number of processors are addressed. We discuss parallelism inherent in the LOVER framework regardless of what enumeration and simulation algorithms are used. Since the enumeration phase is the efficiency bottleneck in parallelizing LOVER-based approaches, we have developed parallel versions of PODEM-based enumeration algorithms. Experimental results are presented to show that high processor utilization can be achieved when these parallelisms are exploited. Speed-up factors of over 7.8 have been achieved with 8 processor configurations.

Personal computer-based dynamic burn-in system

Abstract: An installation for the dynamic burn-in testing of a plurality of digital circuits, and/or microcomputer-controlled circuits, mounted in a burn-in chamber for testing includes a personal computer; power supply for the digital circuits, and a bilateral line of communication between the PC computer and each of the digital circuits; the PC computer interrogating separately, and at will, any of the digital circuits as to their status and capability of changing status while retrieving any indication of a critical testing condition from any digital circuit, to determine a failure-free burn-in time.

Designing for concurrent error detection in VLSI: application to a microprogram control unit

Abstract: An integrated approach to the design of a microprogram control unit (MCU) that possesses the distinction of having comprehensive concurrent-error-detection (CED) capability for errors generated by VLSI physical failures is presented. The implementation of the functionally complex single-chip MCU is discussed and the fault model used is explained. Circuit design techniques that have recently been developed for self-checking VLSI systems are introduced. The first critical appraisal based on actual mask-level layouts of custom CED design versus error detection through duplication and comparison, are also presented.

Using Logic Programming for Fault Diagnosis in Digital Circuits

Abstract: In this paper we show how a Prolog-like logic programming language can be efficiently used for fault diagnosis in digital circuits. We take the approach of diagnosis from first principles, i.e., reasoning from circuit description and behavior. With the single-fault assumption a program written in CHIP, an extended Prolog, locates the faulty gate from a hierarchical description of a circuit and faulty input/output patterns. The fault finding process is modeled in terms of constraint relaxation We show how the introduction of the demon concept in logic programming can improve the consistency checking mechanism and thus makes possible the diagnosis of big circuits. The program was successfully tested on circuits with more than 17000 gates.

Models and logic of MOS circuits

Abstract: Various models of hardware have been proposed though virtually all of them do not model circuits adequately enough to support and provide a formal basis for many of the informal arguments used by designers of MOS circuits. Such arguments use rather crude discrete notions of strength—designers cannot be too finicky about precise resistances and capacitances when building a chip—as well as subtle derived notions of information flow between points in the circuit. One model, that of R. E. Bryant, tackles such issues in reasonable generality and has been used as the basis of several hardware simulators. However Bryant’s model is not compositional. These lectures introduce Bryant’s ideas and present a compositional model for the behaviour of MOS circuits when the input is steady, show how this leads to a logic, and indicate the difficulties in providing a full and accurate treatment for circuits with changing inputs.

Restoring Optical Logic: Demonstration Of Extensible All-Optical Digital Systems

Abstract: We show experimentally how nonlinear all-optical circuit elements can be used to create indefinitely extensible optical logic. By using a "lock and clock" architecture and an off-axis configuration of the power and signal beams, we avoid signal corruption and maintain an undiminished signal level through cascaded devices. Several loop circuits have been operated to simulate an optical classical finite state machine.

Digital Electronics: A Practical Approach

Abstract: (NOTE:Each chapter begins with an Outline, Objectives, and an Introduction, and concludes with a Summary, Glossary, Problems, Schematic Interpretation Problems, Electronics Workbench Exercises, and Answers to Review Questions. ) 1. Number Systems and Codes. Digital Versus Analog. Digital Representations of Analog Quantities. Decimal Numbering System (Base 10). Binary Numbering System (Base 2). Decimal-to-Binary Conversion. Octal Numbering System (Base 8). Octal Conversions. Hexadecimal Numbering System (Base 16). Hexadecimal Conversions. Binary-Coded-Decimal System. Comparison of Numbering Systems. The ASCII Code. Applications of the Numbering System. 2. Digital Electronic Signals and Switches. Digital Signals. Clock Waveform Timing. Serial Representation. Parallel Representation. Switches in Electronic Circuits. A Relay as a Switch. A Diode as a Switch. A Transistor as a Switch. The TTL Integrated Circuit. The CMOS Integrated Circuit. Surface-Mount Devices. 3. Basic Logic Gates. The AND Gate. The OR Gate. Timing Analysis. Enable and Disable Functions. Using IC Logic Gates. Introduction to Troubleshooting Techniques. The Inverter. The NAND Gate. The NOR Gate. Logic Gate Waveform Generation. Using IC Logic Gates. Summary of the Basic Logic Gates and IEEE/IEC Standard Logic Symbols. 4. Programmable Logic Devices: Altera and Xilinx CPLDs and FPGAs. PLD Design Flow. PLD Architecture. Using PLDs to Solve Basic Logic Designs. CPLD Problems. 5. Boolean Algebra and Reduction Techniques. Combinational Logic. Boolean Algebra Laws and Rules. Simplification of Combinational Logic Circuits Using Boolean Algebra. De Morgan's Theorem. The Universal Capability of NAND and NOR Gates. AND-OR-INVERT Gates for Implementing Sum-of-Products Expressions. Karnaugh Mapping. System Design Applications. CPLD Design Applications. CPLD Problems. 6. Exclusive-OR and Exclusive-NOR Gates. The Exclusive-OR Gate. The Exclusive-NOR Gate. Parity Generator/Checker. System Design Applications. CPLD Design Applications. CPLD Problems. 7. Arithmetic Operations and Circuits. Binary Arithmetic. Two's-Complement Representation. Two's-Complement Arithmetic. Hexadecimal Arithmetic. BCD Arithmetic. Arithmetic Circuits. Four-Bit Full-Adder ICs. System Design Applications. Arithmetic/Logic Units. CPLD Design Applications. CPLD Problems. 8. Code Converters, Multiplexers, and Demultiplexers. Comparators. Decoding. Encoding. Code Converters. Multiplexers. Demultiplexers. System Design Applications. CPLD Design Applications. CPLD Problems. 9. Logic Families and Their Characteristics. The TTL Family. TTL Voltage and Current Ratings. Other TTL Considerations. Improved TTL Series. The CMOS Family. Emitter-Coupled Logic. Comparing Logic Families. Interfacing Logic Families. 10. Flip-Flops and Registers. S-R Flip-Flop. Gated S-R Flip-Flop. Gated D Flip-Flop. Integrated-Circuit D Latch (7475). Integrated-Circuit D Flip-Flop (7474). Master--Slave J-K Flip-Flop. Edge-Triggered J-K Flip-Flop. Integrated-Circuit J-K Flip-Flop (7476, 74LS76). Using an Octal D Flip-Flop in a Microcontroller Application. CPLD Problems. 11. Practical Considerations for Digital Design. Flip-Flop Time Parameters. Automatic Reset. Schmitt Trigger ICs. Switch Debouncing. Sizing Pull-Up Resistors. Practical Input and Output Considerations. 12. Counter Circuits and Applications. Analysis of Sequential Circuits. Ripple Counters. Design of Divide-by-N Counters. Ripple Counter ICs. System Design Applications. Seven-Segment LED Display Decoders. Synchronous Counters. Synchronous Up/Down-Counter ICs. Applications of Synchronous Counter ICs. CPLD Design Applications. CPLD Problems. 13. Shift Registers. Shift Register Basics. Parallel-to-Serial Conversion. Recirculating Register. Serial-to-Parallel Conversion. Ring Shift Counter and Johnson Shift Counter. Shift Register ICs. System Design Applications for Shift Registers. Driving a Stepper Motor with a Shift Register. Three-State Buffers, Latches, and Transceivers. CPLD Design Applications. CPLD Problems. 14. Multivibrators and the 555 Timer. Multivibrators. Capacitor Charge and Discharge Rates. Astable Multivibrators. Monostable Multivibrators. Integrated Circuit Monostable Multivibrators. Retriggerable Monostable Multivibrators. Astable Operation of the 555 IC Timer. Monostable Operation of the 555 IC Timer. Crystal Oscillators. 15. Interfacing to the Analog World. Digital and Analog Representations. Operational Amplifier Basics. Binary-Weighted D/A Converters. R/2R Ladder D/A Converters. Integrated-Circuit D/A Converters. Integrated-Circuit Data Converter Specifications. Parallel-Encoded A/D Converters. Counter-Ramp A/D Converters. Successive-Approximation A/D Conversion. Integrated-Circuit A/D Converters. Data Acquisition System Application. Transducers and Signal Conditioning. 16. Semiconductor, Magnetic and Optical Memory. Memory Concepts. Static RAMs. Dynamic RAMs. Read-Only Memories. Memory Expansion and Address Decoding Applications. Magnetic and Optical Storage. 17. Microprocessor Fundamentals. Introduction to System Components and Buses. Software Control of Microprocessor Systems. Internal Architecture of a Microprocessor. Instruction Execution Within a Microprocessor. Hardware Requirements for Basic I/O Programming. Writing Assembly Language and Machine Language Programs. Survey of Microprocessors and Manufacturers. Summary of Instructions. Appendix A. WWW Sites. Appendix B. Manufacturers' Data Sheets. Appendix C. Explanation of the IEEE/IEC Standard for Logic Symbols (Dependency Notation). Appendix D. Answers to Odd-Numbered Problems. Appendix E. CPLD Software Tutorials. Appendix F. Review of Basic Electricity Principles. Appendix G. Schematic Diagrams for Chapter-End Problems. Index. Supplementary Index of ICs.

State of the art in the analog CMOS circuit design

Abstract: This paper is not intended to cover CMOS analog circuit design exhaustively. Yet, it describes how much CMOS technology has been involved in analog circuit design despite the general opinion that CMOS is only suited for digital design. After some developments in the CMOS technology have been discussed, the analog building block scene is covered. The analog building blocks can roughly be divided into two subgroups: the switched-capacitor and the non-switched-capacitor building blocks. Following this subdivision different approaches are briefly looked at. Several tables conclude this review and indicate that new analog developments in CMOS circuit design are still to be expected. Next, the CAD tool development for analog CMOS is discussed, showing that there is still a lot to be done in the field of automated analog design. In conclusion, some ideas concerning analog CAD or, concerning CAD in a more general sense are described.

Switch-Electrical Segmented Waveform Relaxation for Digital MOS VLSI and Its Acceleration on Parallel Computers

Abstract: The Segmented Waveform Relaxation Method (SWRM) is a new and efficient waveform relaxation method for circuit-level simulation of large-scale digital MOS networks. SWRM is original in two aspects. 1) Dynamic feedback loop cutting and waveform event driven scheduling result in a varying simulation order of the subcircuits and, for digital synchronous circuits, lead to logically correct and accurate ground waveforms in one waveform iteration where the only approximation is due to Miller feedback over MOS capacitances (timing error being usually <5 percent). 2) Dynamic decomposition of large subcircuits at MOS transistors which are temporarily in a nonconducting state. SWRM has been implemented in the program SWAN and tested on large industrial circuits (up to 4000 transistors) with speed gains of 10 /spl gt/ 100 over SPICE2G6. A mixed-mode switch electrical implementation of SWRM together with novel acceleration methods on parallel computers will be described together with test results on real-life circuits.

Performance analysis and design of a logic simulation machine

Abstract: The high costs associated with logic simulation of large VLSI circuits has led to the need for new computer architectures tailored to the simulation task. Such architectures have the potential for significant speed-ups over software-based logic simulators executing on standard sequential computers. This paper presents a model of one class of multiprocessor simulation architectures and compares the performance of some of these machines using data obtained from simulations of VLSI circuits. In addition, we discuss the implications of our results on machine design and examine the sensitivity of the model to variations in circuit characteristics.

Precision compressor gain controller in CMOS technology

Abstract: A precision gain-control compressor which makes use of a CMOS compatible lateral bipolar transistor is described. Two similar circuits are presented that enable raises to positive as well as negative powers. These circuits are specifically designed for use in CMOS hearing-aid systems.

Parity check logic circuit

Abstract: A multiple-input logic circuit for carrying out an even parity check operation or an odd parity check operation on a plurality of input signals has such a circuit construction that a signal only passes through a maximum of essentially two gates between an input and an output of the multiple-input logic circuit, so as to increase the operation speed and reduce the number of elements constituting the multiple-input logic circuit.

Switch-Level Logic Simulation of Digital Bipolar Circuits

Abstract: This paper describes a new approach for logic simulation of bipolar digital circuits. The approach is based on the development of a switch-level model of the transistor and on representing the circuit by a switch-graph. The method automatically partitions the circuit into subcircuits, and symbolic logic expressions are then generated which represent the logic states of the nodes in terms of subcircuit inputs and initial conditions. The method thus extracts a gate-level functional description of the circuit from transistor netlist or layout. Logic and fault simulation can then be performed using either extracted logic expressions or the switch-graph model. The approach has been implemented in a computer program for logic simulation of common-mode logic (CML) bipolar circuit designs.

A Logic Simulator to Support Design Instruction

Abstract: Digital and computer systems have received increased attention in recent years, and it has become necessary to introduce more digital design into already busy undergraduate electrical engineering programs. This paper describes a very simple digital hardware logic simulator that is in use to expand the undergraduate digital design education without increasing the student's work load. The student is exposed to the concept of digital hardware simulation in addition to the usual studies in digital logic design. This addition of simulation requires limited additional effort, and it reduces the laboratory debugging effort required of the novice designer. Substantial error checking is included to encourage good design practice. The simulator runs on several computers including various personal computers.

Specification and verification of asynchronous circuits using marked graphs

Abstract: This paper deals with the behavioral specification and description of digital circuits operating asynchronously. In particular, it is shown how the behavior of a composite circuit may be derived from the behavioral description of its components. The paper combines the theory of trace structures developed by M. Rem and J.L.A. van de Snepsheut with a suitable extension of the theory of marked graphs. It consequently achieves a considerable simplification of the way composite circuits are modeled and verified.

Applications of multi-valued logic to testing of binary and MVL circuits

Abstract: Binary linear feedback shift registers (LFSR's) have acquired great importance in their implementation of a method of data compaction used in the testing of digital circuits. In this paper a new idea is examined: using multiple-valued LFSR's for the testing of MVL circuits and of binary circuits. For MVL circuits a non-binary LFSR avoids the need of decoding the signals and its implementation requires fewer digits than the binary tester. For binary circuits, a multi-valued LFSR tester shows higher effectiveness while maintaining a smaller implementation. An analysis is given of fault coverage for binary and multi-valued circuits, and optimal implementations of multi-valued LFSR's are presented.