Showing papers on "Digital electronics published in 1998"

Digital circuit applications of resonant tunneling devices

Abstract: Many semiconductor quantum devices utilize a novel tunneling transport mechanism that allows picosecond device switching speeds The negative differential resistance characteristic of these devices, achieved due to resonant tunneling, is also ideally suited for the design of highly compact, self-latching logic circuits As a result, quantum device technology is a promising emerging alternative for high-performance very-large-scale-integration design The bistable nature of the basic logic gates implemented using resonant tunneling devices has been utilized in the development of a gate-level pipelining technique, called nanopipelining, that significantly improves the throughput and speed of pipelined systems The advent of multiple-peak resonant tunneling diodes provides a viable means for efficient design of multiple-valued circuits with decreased interconnect complexity and reduced device count as compared to multiple-valued circuits in conventional technologies This paper details various circuit design accomplishments in the area of binary and multiple-valued logic using resonant tunneling diodes (RTD's) in conjunction with high-performance III-V devices such as heterojunction bipolar transistors (HBT's) and modulation doped field-effect transistors (MODFET's) New bistable logic families using RTD+HBT and RTD+MODFET gates are described that provide a single-gate, self-latching majority function in addition to basic NAND, NOR, and inverter gates

Introduction to mechatronics and measurement systems

Abstract: 1 Introduction 2 Electric Circuits and Components 3 Semiconductor Electronics 4 System Response 5 Analog Signal Processing Using Operational Amplifiers 6 Digital Circuits 7 Microcontroller Programming and Interfacing 8 Data Acquisition 9 Sensors 10 Actuators 11 Mechatronic Systems-Control Architectures and Case Studies Appendixes A Measurement Fundamentals B Physical Principles C Mechanics of Materials

Dynamically reconfigurable logic networks interconnected by fall-through FIFOs for flexible pipeline processing in a system-on-a-chip

Abstract: An integrated circuit comprising a plurality of reconfigurable logic networks, one or more buffers, a configuration control network, and an embedded processor, all comprised as an integral part of the integrated circuit, and a method of operation of the integrated circuit One or more of the buffers are coupled between two of the plurality of reconfigurable logic networks The buffers isolate the plurality of reconfigurable logic networks from one another The integration control network is coupled to each of the plurality of reconfigurable logic networks, and may also be coupled to one or more buffers The embedded processor is operable to reconfigure one or more of the plurality of reconfigurable logic networks over the configuration control network The integrated circuit may also comprise a local memory The local memory is coupled to the embedded processor, and is operable to store data and/or instructions accessible by the embedded processor A logic configuration library may also be comprised on the integrated circuit The logic configuration library is coupled to the embedded processor and is further coupled to the configuration control network The logic configuration library is operable to store one more configurations for the plurality of reconfigurable logic networks The reconfigurable logic networks preferably include at least a first logic network and a second logic network

SOI for digital CMOS VLSI: design considerations and advances

Abstract: This paper reviews the recent advances of silicon-on-insulator (SOI) technology for complementary metal-oxide-semiconductor (CMOS) very-large-scale-integration memory and logic applications. Static random access memories (SRAMs), dynamic random access memories (DRAMs), and digital CMOS logic circuits are considered. Particular emphases are placed on the design issues and advantages resulting from the unique SOI device structure. The impact of floating-body in partially depleted devices on the circuit operation, stability, and functionality are addressed. The use of smart-body contact to improve the power and delay performance is discussed, as are global design issues.

CMOS circuit design of threshold gates with hysteresis

Abstract: M-of-N threshold gates with hysteresis form a class of circuit elements that have important application in NULL Convention Logic/sup TM/, a novel asynchronous logic design methodology. General design guidelines for these M-of-N gates are presented using CMOS technology. Three types of circuit implementations are discussed: static, semi-static and dynamic. In addition, initialization techniques are presented for use in establishing a known initial state.

Modeling and comparing CMOS implementations of the C-element

Abstract: Various applications have demonstrated that asynchronous circuits have great potential for energy-efficient and high-performance design. One of the primitives used in asynchronous control circuits is the C-element. Analytical delay and energy models are presented and applied to the most popular complementary metal-oxide-semiconductor (CMOS) implementations of the C-element. Optimization of these implementations are discussed. The implementations are also compared using simulations. The simulation results are in good agreement with the analytical predictions.

Method for verification of combinational circuits using a filtering oriented approach

Abstract: A set of filters are arranged in sequence for verification and analysis of digital circuit designs. The filters are either active filters, which are directly involved in verification of circuit designs (e.g., a Binary Decision Diagram (BDD)-based verifier or an automatic test pattern generation (ATPG)-based verifier), or passive filters, which gather information about the circuit or transform the circuit structure in order to simplify the verification problem (e.g., random pattern simulation or circuit partitioning). Given a pair of circuits to be verified, the filter approach first subjects the circuits to very simple, fast techniques having very low memory usage requirements. These steps are followed by a series of increasingly powerful methods that are more time consuming and often require more computer memory for their operation. In between the simpler active filters and the more sophisticated active filters, information about potential equivalent nodes in the circuits is collected and a decision is made as to whether to partition the circuits. The verification methodology is structured such that circuit designs that are easier to verify are never unnecessarily subjected to more expensive techniques. The method provides for a gradual increase in the sophistication of verification techniques applied, according to the difficulty of the verification problem.

High density and high speed magneto-electronic logic family

Abstract: A number of novel new devices and circuits are disclosed utilizing configurable magneto-electronic elements such as magnetic spin transistors and hybrid hall effect devices. Such magneto-electronic elements can be used as building blocks of an entirely new family of electronic devices for performing functions not easily implementable with semiconductor based device. A number of examples are provided, including logic gates that can be programmed to perform different boolean logic operations at different periods of time. Logic devices and circuits incorporating such logic gates have a number of operational advantages and benefits over conventional semiconductor based technologies, including the fact that traditional signal logic operations can be implemented with substantially fewer active elements. A conventional boolean function unit, for example, can be constructed with 2 magneto-electronic elements, and 2 semiconductor elements, which is a 400% improvement over prior art pure semiconductor based technologies.

Resonant-tunneling diode and HEMT logic circuits with multiple thresholds and multilevel output

Abstract: By using resonant-tunneling diodes (RTDs) and high electron mobility transistors (HEMTs), we implement a new class of logic circuits that operate with multiple thresholds and multilevel output. The basic idea of the circuits is to synthesize transfer characteristics by key logic elements, namely, up and down literals. We first describe two fundamental logic circuits based on this idea: a ternary inverter and a literal gate. Then we present experimental results on these circuits fabricated by integrating InP-based RTDs and HEMTs. It is found that these circuits operate successfully with threshold voltages and output levels that have been predicted from individual device characteristics. Consequently, the validity of the basic idea behind the circuits presented here is proven. The device counts and the number of logic stages required for the present circuits are less than half those for conventional ones. A possible application is finally discussed.

Method for verifying and representing hardware by decomposition and partitioning

Abstract: A system and method for representing digital circuits and systems in multiple partitions of Boolean space, and for performing digital circuit or system validation using the multiple partitions. Decision diagrams are built for the digital circuit or system and pseudo-variables are introduced at decomposition points to reduce diagram size. Pseudo-variables remaining after decomposition are composed and partitioned to represent the digital circuit or system as multiple partitions of Boolean space. Each partition is built in a scheduled order, and is manipulable separately from other partitions.

Fingerprinting Digital Circuits on Programmable Hardware

Abstract: Advanced CAD tools and high-density VLSI technologies have combined to create a new market for reusable digital designs. The economic viability of the new core-based design paradigm is pending on the development of techniques for intellectual property protection. A design watermark is a permanent identification code that is difficult to detect and remove, is an integral part of the design, and has only nominal impact on performances and cost of design. Field Programmable Gate Arrays (FPGAs) present a particularly interesting set of problems and opportunities, because of their flexibility. We propose the first technique that leverages the unique characteristics of FPGAs to protect commercial investment in intellectual property through fingerprinting. A hidden encrypted message is embedded into the physical layout of a digital circuit when it is mapped into the FPGA. This message uniquely identifies both the circuit origin and original circuit recipient, yet is difficult to detect and or remove. While this approach imposes additional constraints on the back-end CAD tools for circuit place and route, experiments involving a number of industrial-strength designs indicate that the performance impact is minimal.

On Discretization of Delays in Timed Automata and Digital Circuits

Abstract: In this paper we solve the following problem: “given a digital circuit composed of gates whose real-valued delays are in an integer-bounded interval, is there a way to discretize time while preserving the qualitative behavior of the circuit?” This problem is described as open in [BS94]. When “preservation of qualitative behavior” is interpreted in a strict sense, as having all original sequences of events with their original ordering we obtain the following two results: 1) For acyclic (combinatorial) circuits whose inputs change only once, the answer is positive: there is a constant δ, depending on the maximal number of possible events in the circuit, such that if we restrict all events to take place at multiples of δ, we still preserve qualitative behaviors. 2) For cyclic circuits the answer is negative: a simple circuit with three gates can demonstrate a qualitative behavior which cannot be captured by any discretization.

Issue logic for a 600-MHz out-of-order execution microprocessor

Abstract: The logic and circuits are presented for a 20-entry instruction queue which scoreboards 80 registers and issues four instructions per cycle in a 600-MHz microprocessor. The request logic and arbiter circuits that control integer execution are described in addition to a novel compaction scheme that maintains temporal order in the queue. The issue logic data path is implemented in 141000 transistors, occupying 10 mm/sup 2/ in a 0.35-/spl mu/m CMOS process.

Automatic test pattern generation for crosstalk glitches in digital circuits

Abstract: As clock speeds of current deep submicron design technologies increase over 1 GHz and metal line spacings narrow, unexpected crosstalk effects start to degrade the circuit performance significantly. It is important for the designer to test the effects before taping out the designs. Unfortunately, conventional tests for stuck-at or delay faults are not guaranteed to expose potential crosstalk effects. This paper presents an efficient methodology for generating test vectors to detect crosstalk glitch effects in digital circuits. The ATEG (Automatic Test Extractor for Glitch) algorithm uses the multiple backrace technique, and uses a "forward-evaluation" technique in its backtacking phase which searches for the "right" entry to select by propagating "suggested values" to minimize the number of backtracks. In the glitch propagation phase, we employ a criterion function which gives a metric for determining the propagation of a transitional signal at a given gate. Our experiments show that ATEG efficiently generates test vectors to create glitches at candidate nodes.

Microtechnology in the development of three-dimensional circuits

Abstract: With today's cost-conscience industry, low cost, high-performance, and high-profit microwave-circuit technologies are essential. To increase density and reduce size and cost, the integration of analog and digital circuits on one single chip is considered the most viable solution. In reducing the size of the overall system, high-density integration (HDI) and packaging have become critical components in circuit design. This paper reviews and evaluates state-of-the-art planar transmission lines and vertical interconnects for use in high-density multilayer circuits for silicon- and SiGe-based monolithic high-frequency circuits. Packaging issues associated with parasitics are discussed and examples of multilayer three-dimensional systems utilizing micromachining are presented.

Aspects of Digital Evolution: Geometry and Learning

Abstract: In this paper we present a new chromosome representation for evolving digital circuits. The representation is based very closely on the chip architecture of the Xilinx 6216 FPGA. We examine the effectiveness of evolving circuit functionality by using randomly chosen examples taken from the truth table. We consider the merits of a cell architecture in which functional cells alternate with routing cells and compare this with an architecture in which any cell can implement a function or be merely used for routing signals. It is noteworthy that the presence of elitism significantly improves the Genetic Algorithm performance.

Noise considerations in circuit optimization

Abstract: Noise can cause digital circuits to switch incorrectly and thus produce spurious results. Noise can also have adverse power, timing and reliability effects. Dynamic logic is particularly susceptible to charge-sharing and coupling noise. Thus, the design and optimization of a circuit should take noise considerations into account. Such considerations are typically stated as semi-infinite constraints. In addition, the number of signals to be checked and the number of sub-intervals of time during which the checking must be performed can potentially be very large. Thus, the practical incorporation of noise constraints during circuit optimization is a hitherto unsolved problem. This paper describes a novel method for incorporating noise considerations during automatic circuit optimization. Semi-infinite constraints representing noise considerations are first converted to ordinary equality constraints involving time integrals, which are readily computed in the context of circuit optimization based on time-domain simulation. Next, the gradients of these integrals are computed by the adjoint method. By using an augmented Lagrangian optimization merit function, the adjoint method is applied to compute all the necessary gradients required for optimization in a single adjoint analysis, no matter how many noise measurements are considered, and irrespective of the dimensionality of the problem. Numerical results are presented.

Characterization and parameterized generation of synthetic combinational benchmark circuits

Abstract: The development of new field-programmed, mask-programmed, and laser-programmed gate-array architectures is hampered by the lack of realistic test circuits that exercise both the architectures and their automatic placement and routing algorithms. In this paper, we present a method and a tool for generating parameterized and realistic synthetic circuits. To obtain the realism, we propose a set of graph-theoretic characteristics that describe a physical netlist, and have built a tool that can measure these characteristics on existing circuits. The generation tool uses the characteristics as constraints in the synthetic circuit generation. To validate the quality of the generated netlists, parameters that are not specified in the generation are compared with those of real circuits and with those of more "random" graphs.

Digital circuit layout techniques

Abstract: A technique for analyzing digital circuits to identify pin swaps is provided for circuit layout and similar tasks in which the circuit is first decomposed into fanout-free regions. Quasi-canonical forms or models of the fanout free region are created from which a swap structure is created so that pins swap groups can be identified.

Clock-controlled neuron-MOS logic gates

Abstract: A new clock-controlled circuit scheme has been introduced in the basic architecture of neuron-MOS (neuMOS or /spl nu/MOS) logic gates. In this scheme, the charge on a neuMOS floating gate is periodically refreshed by a clock-controlled switch. A special refreshing scheme in which fluctuations in device parameters are automatically canceled has been employed. As a result, the number of multiple logic levels that can be handled in a neuMOS floating gate has been increased. In addition, the data subtraction operation directly conducted on the floating gate has become possible. All of these circuit techniques have enhanced the functionality of a neuMOS logic gate a great deal. In order to achieve a low power operation, latched-sense-amplifier circuitries are also introduced for logic decision. Test circuits were fabricated in a double-polysilicon CMOS process, and the basic circuit operations are demonstrated.

Evolving Digital Logic Circuits on Xilinx 6000 Family FPGAs

Abstract: This paper describes work which attempts to evolve circuit solutions for combinational logic systems directly onto Xilinx 6000 FPGA parts. The reason for attempting to evolve designs direct onto the device is twofold: (i) every circuit has a known functionality and (ii) every circuit must be able to be placed on the chip and then routed. Using evolutionary techniques allows us to consider these two important aspects of design and implementation as a single problem. The paper describes the basic method adopted, using a network list (netlist) chromosome and genes which represent circuit module function, and then discusses some of the results achieved, plus difficulties encountered, and some of the additional problems which still require to be solved in this new and exciting area of research.

Single-electron-parametron-based logic devices

Abstract: We analyze the operation of the wireless single-electron logic family based on single-electron-parametron cells. Parameter margins, energy dissipation, and the error probability are calculated using the orthodox theory of single-electron tunneling. Circuits of this family enable quasireversible computation with energy dissipation per bit much lower than the thermal energy, and hence may circumvent one of the main obstacles faced by ultradense three-dimensional integrated digital circuits.

Technology mapping for large complex PLDs

Abstract: In this paper we present a new technology mapping algorithm for use with complex PLDs (CPLDs), which consists of a large number of PLA-style logic blocks. Although the traditional synthesis approach for such devices uses two-level minimization, the complexity of recently-produced CPLDs has resulted in a trend toward multi-level synthesis. We describe an approach that allows existing multi-level synthesis techniques [13] to be adapted to produce circuits that are well-suited for implementation in CPLDs. Our algorithm produces circuits that require up to 90% fewer logic blocks than the circuits produced by a recently-published algorithm.

Ones and Zeros: Understanding Boolean Algebra, Digital Circuits, and the Logic of Sets

Abstract: From the Publisher: Ones and Zeros explains, in lay terms, Boolean algebra, the suprisingly simple system of mathematical logic used in digital computer circuitry. Ones and Zeros follows the development of this logic system from its origins in Victorian England to its rediscovery in this century as the foundation of all modern computing machinery. Readers will learn about the interesting history of the development of symbolic logic in particular, and the often misunderstood process of mathematical invention and scientific discovery, in general. Ones and Zeros also features practical exercises with answers, real-world examples of digital circuit design, and a reading list. Ones and Zeros will be of particular interest to software engineers who want to gain a comprehensive understanding of computer hardware. Outstanding features include: a history of mathematical logic, an explanation of the logic of digital circuits, and hands-on exercises and examples.

Programmable digital circuits

Abstract: A composite digital network including an integrating circuit, a summing circuit and a coefficient circuit is formed as an integrated circuit that provides a selected one of digital arithmetic circuits that perform different arithmetic operations depending upon coefficients of the coefficient circuits. A plurality of units of such composite digital networks may be connected in rows, columns or layers to provide an expanded network. In a method of producing such a composite digital network, basic digital arithmetic circuits that respectively correspond to various types of basic analog arithmetic circuits are defined based on Kirchhoff's rules, for example, and these basic digital arithmetic circuits are coupled to each other via a coefficient circuit to thus provide a generic digital arithmetic integrated circuit.

Digital oscillation-test method for delay and stuck-at fault testing of digital circuits

Abstract: Testing delay faults is becoming critical in new deep submicron digital circuits. This paper introduces a new technique for delay and stuck-at fault testing in digital integrated circuits. The proposed technique consists of sensitizing a path in the digital circuit under test and then incorporating it in a ring oscillator to test for delay and stuck-at faults in the path. This procedure should be exercised for all or at least critical paths in the circuit. To establish oscillations, we should make sure that there is an odd number of inverters in the loop. This technique can be used along with scan techniques or be implemented as a built-in self-test technique. Benchmark results confirm the efficiency of the proposed technique. The technique has been implemented in practice for an an 8-bit digital adder on a field programmable device.

Method and apparatus for a N-nary logic circuit using 1 of 4 signals

Abstract: The present invention is a method and apparatus for a N-nary logic circuit that comprises a logic tree circuit that couples to a first set of input logic paths, a second set of input logic paths, and a set of output logic paths, which all use 1 of N signals where one and only one of the N logic paths is active during an evaluation cycle. The preferred embodiment of the present invention uses 1 of 4 signals, while other embodiments of present invention include 1 of 2 signals, 1 of 3 signals, 1 of 8 encoding, and the general embodiment of the 1 of N signals. The logic tree circuit evaluates a given function that includes, for example, an AND/NAND function, an OR/NOR function, or an XOR/Equivalence function. The logic tree circuit uses a single, shared logic tree with multiple evaluation paths for evaluating the function of the logic circuit.

Dynamic digital integrated circuit testing using oscillation-test method

Abstract: A new technique to deal with simultaneous testing of delay and stuck-at faults in digital integrated circuits is proposed. It consists of sensitising a path in the digital circuit under test and then incorporating it in a ring oscillator to test for delay and stuck-at faults in the path. This procedure should be exercised for all, or at least critical, paths in the circuit. This test technique can be used along with scan techniques or implemented as a complete built-in self-test solution.

QMOS digital logic circuits

Abstract: Circuit designs of basic digital logic gates are disclosed using Resonant Tunneling Diodes (TRDs) (620, 670) and MOSFETs (600, 605, 615, 625, 630, 640, 655, 660, 665, 675, 680) which reduces the number of devices used for logic design, while exploiting the high speed negative differential resistance (NDR) characteristic of RTDs. Such logic circuits include NAND, NOR, AND, and OR gates and Minority/Majority circuits, which are used in full adder circuits. By implementing RTDs along with conventional MOSFETs, the use of series connected MOSFETs, which results in low output rise and fall times, especially for a large number of inputs, can be avoided. Furthermore, the RTD logic design styles do not require the use of resistors or any elaborate clocking or resetting scheme.

Design considerations for integrated continuous-time chaotic oscillators

Abstract: This paper presents an optimization procedure to choose the chaotic state equation which is best suited for implementation using Gm-C integrated circuit techniques. The paper also presents an analysis of the most significant hardware nonidealities of Gm-C circuits on the chaotic operation-the basis to design robust integrated circuits with reproducible and easily controllable behavior. The techniques in the paper are illustrated through a circuit fabricated in 2.4-/spl mu/m double-poly technology.