Showing papers on "Digital electronics published in 2002"

Digital processing and communication with molecular switches

Abstract: The tremendous pace in the development of information technology is rapidly approaching a limit. Alternative materials and operating princlples for the elaboration and communication of data in electronic circults and optical networks must be identified. Organic molecules are promising candidates for the realization of future digital processors. Their attractive features are the miniaturized dimensions and the high degree of control on molecular design possible in chemical synthesis. Indeed, nanostructures with engineered properties and specific functions can be assembled relying on the power of organic synthesis. In particular, certain molecales can be designed to switch from one state to another, when addressed with chemical, electrical, or optical stimulations, and to produce a detectable signal in response to these transformations. Binary data can be enceded on the input stimulations and output signals employing logic conventions and assumptions similar to those ruting digital electronics. Thus, binary inputs can be transduced into binary outputs relying on molecular switches. Following these design principles, the three basic logic operations (AND, NOT, and OR) and more complex logic functions (EOR, INH, NOR, XNOR, and XOR) have been reproduced already at the molecular level. Presently, these simple "molecular processors" are far from any practical application. However, these encouraging results demonstrate already that chemical systems can process binary data with designed logic protocols. Further fundamental studies on the various facets of this emerging area will reveal if and how molecular switches can become the basic components of furture logic devices. After all, chemical computers are available atready. We all carry one in our head!

A dynamic and differential CMOS logic with signal independent power consumption to withstand differential power analysis on smart cards

Abstract: To protect security devices such as smart cards against power attacks, we propose a dynamic and differential CMOS logic style. The logic operates with a power consumption independent of both the logic values and the sequence of the data. Consequently, it will not reveal the sensitive data in a device. We have built a set of logic gates and flip-flops needed for cryptographic functions and compared those to Static Complementary CMOS implementations.

Gate-diffusion input (GDI): a power-efficient method for digital combinatorial circuits

Abstract: Gate diffusion input (GDI) - a new technique of low-power digital combinatorial circuit design - is described. This technique allows reducing power consumption, propagation delay, and area of digital circuits while maintaining low complexity of logic design. Performance comparison with traditional CMOS and various pass-transistor logic design techniques is presented. The different methods are compared with respect to the layout area, number of devices, delay, and power dissipation. Issues like technology compatibility, top-down design, and precomputing synthesis are discussed, showing advantages and drawbacks of GDI compared to other methods. Several logic circuits have been implemented in various design styles. Their properties are discussed, simulation results are reported, and measurements of a test chip are presented.

Impact of spatial intrachip gate length variability on the performance of high-speed digital circuits

Abstract: In this paper we address both empirically and theoretically the impact of an advanced manufacturing phenomenon on the performance of high-speed digital circuits. Using data collected from an actual state-of-the-art fabrication facility, we conducted a comprehensive characterization of an advanced 0.18-/spl mu/m CMOS process. The measured data revealed a significant systematic, rather than random spatial intrachip variability of MOS gate length, leading to large circuit path delay variation. The delay of the critical path of a combinational logic block varies by as much as 17%, and the global skew is increased by 8%. Thus, a significant timing error and performance loss takes place if variability is not properly addressed. We derive a model, which allows estimating performance degradation for the given circuit and process parameters. We demonstrate explicitly that intrachip Lgate variation has a significant detrimental impact on the overall circuit performance, shifting the entire distribution of clock frequencies toward slower values. This is in striking contrast to the impact of interchip Lgate variation, traditionally considered in statistical circuit analysis, which leads to the variation of chip clock frequencies around the average value. Moreover, analysis shows that the spatial, rather than proximity-dependent systematic Lgate variability, is the main cause of large circuit speed degradation. The degradation is worse for the circuits with a larger number of critical paths and shorter average logic depth. We propose a location-dependent timing analysis methodology that allows mitigation of the detrimental effects of Lgate variability and have developed a tool linking the layout-dependent spatial information to circuit analysis. We discuss the details of practical implementation of the methodology, and provide guidelines for managing design complexity.

Logic synthesis of reversible wave cascades

Abstract: A circuit is reversible if it maps each input vector into a unique output vector, and vice versa. Reversible circuits lead to power-efficient CMOS implementations. Reversible logic synthesis may be applicable to optical and quantum computing. Minimizing garbage bits is the main challenge in reversible logic synthesis. This paper introduces an algorithm to generate the cascade of reversible complex Maitra terms (called here reversible wave cascade) implementing incompletely specified Boolean functions. The remarkable property of the presented method compared to other reversible synthesis methods is that it creates at most one constant input and no additional garbage outputs. Preliminary estimation suggests that the method may be applicable to small and medium-sized benchmarks.

Toward in vivo Digital Circuits

Abstract: We propose a mapping from digital logic circuits into genetic regulatory networks with the following property: the chemical activity of such a genetic network in vivo implements the computation specified by the corresponding digital circuit. Logic signals are represented by the synthesis rates of cytoplasmic DNA binding proteins. Gates consist of structural genes for output proteins, fused to promoter/operator regions that are regulated by input proteins. The modular approach for building gates allows a free choice of signal proteins and thus enables the construction of complex circuits. This paper presents simulation results that demonstrate the feasibility of this approach. Furthermore, a technique for measuring gate input/output characteristics is introduced. We will use this technique to evaluate gates constructed in our laboratory. Finally, this paper outlines automated logic design and presents BioSpice, a prototype system for the design and verification of genetic digital circuits.

Duet: an accurate leakage estimation and optimization tool for dual-V/sub t/ circuits

Abstract: Presents a new approach for the estimation and optimization of standby power dissipation in large MOS digital circuits. We introduce a new approach for accurate and efficient calculation of the average standby or leakage current in large digital circuits by introducing the concepts of "dominant leakage states" and the use of state probabilities. Combined with graph reduction techniques and simplified nonlinear simulation, the method achieves speedups of three to four orders of magnitude over exhaustive SPICE simulations while maintaining very good accuracy. The leakage current calculation is then utilized in a new leakage and performance optimization algorithm for circuits using dual V/sub t/ processes. The approach is the first to consider the assignment of both the V/sub t/ and the width of a transistor, simultaneously. The optimization approach uses incremental calculation of leakage and performance sensitivities and can take into account a partially defined circuit state constraint for the standby mode of the device.

Power gain in a quantum-dot cellular automata latch

Abstract: We present an experimental demonstration of power gain in quantum-dot cellular automata (QCA) devices. Power gain is necessary in all practical electronic circuits where power dissipation leads to decay of logic levels. In QCA devices, charge configurations in quantum dots are used to encode and process binary information. The energy required to restore logic levels in QCA devices is drawn from the clock signal. We measure the energy flow through a clocked QCA latch and show that power gain is achieved.

A "digital" 6-bit ADC in 0.25-μm CMOS

Abstract: Traditionally, circuit designers have adopted analog techniques to overcome comparator offset in flash converters. These schemes usually have an adverse effect on area and power consumption, and more seriously do not scale easily to low voltage processes. We describe a digital technique, which removes the accuracy constraints from the comparators. With no analog matching requirement, the comparators can be small, fast and power efficient. A 6-bit prototype converter built in a standard 0.25~ digital CMOS process occupies 1.2mm2 and dissipates llOmW from a 2.2V supply at 300Ms/s.

Methodology and experimental verification for substrate noise reduction in CMOS mixed-signal ICs with synchronous digital circuits

Abstract: This paper describes substrate noise reduction techniques for synchronous CMOS circuits. Low-noise digital design techniques have been implemented and measured on a mixed-signal chip, fabricated in a 0.35 /spl mu/m CMOS process on an EPI-type substrate with 10 /spl Omega/cm EPI resistivity and 4 /spl mu/m EPI layer thickness. The test chip contains one reference design and two digital low-noise designs with the same basic architecture. Measurements show more than a factor of 2 on average in r.m.s. noise reduction with penalties of 3% in area and 4% in power for the low-noise design employing a supply-current waveform-shaping technique based on a clock tree with latencies. The second low-noise design employing separate substrate bias for both n- and p-wells, dual-supply, and on-chip decoupling achieves more than a factor of 2 reduction in r.m.s. noise, with, however, a 70% increase in area, but with a 5% decrease in power consumption.

Semiconductor integrated circuit device

Abstract: PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit device which realizes rapidity of transition to a reset state in a RESET period while keeping rapidity of state transition in an EVALUATE period, and has a digital circuit part such as PSCMOS circuit which enables further rapid operation. SOLUTION: A reset circuit 21 is connected between an output net OUT and a power supply voltage VDD and is constituted of a PMOS transistor MP5 controlled by a reset signal R to a gate terminal, and is added to a PSCMOS type 4-input NOR circuit 11 which carries out NOR logic operation at a fast speed in an EVALUATE period. In a RESET period, control is carried out by a reset signal R, and thereby the PMOS transistor MP5 is made conductive and an output net OUT is charged with a power supply voltage VDD at a fast speed. As a result, an output net OUT of the PSCMOS type 4-input NOR circuit 11 is changed to a reset state and fast circuit operation is carried out.

Fast RNS FPL-based Communications Receiver Design and Implementation

Abstract: Currently, several design barriers inhibit the implementation of high-precision digital signal processing (DSP) systems with field programmable logic (FPL) devices A new demonstration of the synergy between the residue number system (RNS) and FPL technology is presented in this paper The quantifiable benefits of this approach are studied in the context of a high-end communications digital receiver A new RNS-based direct digital synthesizer (DDS) that does not need a scaler circuit is introduced The programmable decimation FIR filter is based on the arithmetic benefits associated with Galois fields and supports tuning the IF frequency as well as its bandwidth Results show the proposed methodology requires fewer resources than classical designs, while throughput advantage is about 65%

Digital configurable macro architecture

Abstract: A new digital configurable macro architecture is described. The digital configurable macro architecture is well suited for microcontroller or controller designs. In particular, the foundation of the digital configurable macro architecture is a programmable digital circuit block. In an embodiment, programmable digital circuit blocks are 8-bit circuit modules that can be programmed to perform any one of a variety of predetermined digital functions by changing the contents of a few registers therein, unlike a FPGA which is a generic device that can be programmed to perform any arbitrary digital function. Specifically, the circuit components of the programmable digital circuit block are designed for reuse in several of the predetermined digital functions such that to minimize the size of the programmable digital circuit block.

A "flying-adder" architecture of frequency and phase synthesis with scalability

Abstract: Most of today's digital designs, from small-scale digital block designs to system-on-chip (SoC) designs, are based on "synchronous" design principle. Clock is the most important issue in these designs. Frequency and phase synthesis is closely related to the clock generation. A frequency and phase synthesis technique based on phase-locked loop is proposed in that delivers high performance, easy integration, and high stability. However, there are problems associated with this architecture, such as: 1) its highest deliverable frequency is limited by the speed of the accumulator and 2) the phase synthesis circuitry will not work well in certain ranges (dead zone) and in certain conditions (dual stability). This paper presents an improved architecture that addresses these problems. The new frequency synthesis circuitry has scalability for higher output frequency. It also has an internal node whose frequency is twice that of output signal. When duty cycle is not a concern, this signal can be used directly as clock source. The new phase synthesis circuitry is free of "dead zone" and "dual stability." The improved architecture has better performance, is simpler to implement, and is easier to understand.

Bit-stream signal processing and its application to communication systems

Abstract: The paper describes a digital circuit technique to process directly bit-stream signals from sigma-delta modulation based analogue-to-digital converters and the application of the technique to communication systems. The newly developed adder and multiplier are fundamental processing circuit modules. Using the fundamental modules and up/down counters, other circuit modules, such as oscillators, dividers and square root circuits, can also be realised. Signal processors built from the modules have three advantages over multi-bit Nyquist rate processors. First, single-bit/multibit converters are not needed at the inputs of the processors because the arithmetic modules directly process the bit-stream signals. Secondly, the physical areas for routing the signals among the circuit modules are small since they are in the form of a bit-stream. Thirdly, the processors are built from a smaller number of logic gates than conventional Nyquist rate processors because of the simple structure of the circuit modules. As an application of the technique to digital signal processing for communications, a QPSK demodulator is presented. In addition to circuit simulations of the demodulator, a useful linear analysis to estimate the influence of the noise components contained in the outputs from the circuit modules on the steady-state demodulation performance is explained.

Gate-diffusion input (GDI) - a technique for low power design of digital circuits: analysis and characterization

Abstract: GDI (Gate Diffusion Input) - a new technique of low power digital circuit design is described. This technique allows reducing power consumption, delay and area of digital circuits, while maintaining low complexity of logic design. Performance comparison with traditional CMOS and various PTL design techniques is presented, with respect to the layout area, number of devices, delay and power dissipation, showing advantages and drawbacks of GDI as compared to other methods. A variety of logic gates have been implemented in 0.35 /spl mu/m technology to compare the GDI technique with CMOS and PTL. A prototype test chip of 8-bit CLA adder has been fabricated, based on GDI and CMOS cell libraries, showing up to 45% reduction in power-delay product in GDI. Properties of implemented circuits are discussed, simulation results are reported and measurements of a test chip are presented.

Field-Programmable Analog Arrays: A Floating-Gate Approach

Abstract: Floating-gate analog circuits are being used to implement advanced signal processing functions and are very useful for processing analog signals prior to analog to digital conversion. We present an architecture analogous to FPGA architectures for rapid prototyping of analog signal processing systems. These systems go beyond simple programmable amplifiers and filters to include programmable and adaptive filters, multipliers, gains, winner-take-all circuits, and matrix-array signal operations. We discuss architecture as well as details such as switching characteristics and interfacing to digital circuits or FPGAs.

Implementation of microprogrammed control in FPGAs

Abstract: The microprogrammed approach to implementing control state machines has been widely used since the early 1960s and has the advantages of structured programming and fixed timing characteristics. This paper presents a microprogrammed control unit that has been tailored to implementation in field-programmable gate arrays (FPGAs). The microsequencer has a novel architecture which takes advantage of the enhancements existing in coarse-grained FPGAs to implement efficiently four basic functions: registers, multiplexers, adders, and counters. The sequencer supports both nested subroutines and nested loops, and can operate in both pipelined and nonpipelined modes. The pipelined mode of operation uses delayed branching in which one additional microinstruction always executes following any instruction that changes program flow. It is found that in a typical medium-sized (50 K gates) FPGA, the sequencer can be clocked at over 60 MHz nonpipelined and over 100 MHz pipelined while using less than 5% of the available FPGA logic resources. This leaves the bulk of the FPGA resources available for implementing other digital circuitry that is to be controlled by the microsequencer. While not attractive for a small number of states, the microprogrammed approach has some significant advantages for complex controllers with a large number of states.

Cooperative analog-digital signal processing

Abstract: We introduce the concept of cooperative analog-digital signal processing, and its implications on real-time signal processing functions We discuss some of the trade-offs between performing operations in the analog computing circuit and digital computing circuits, and a general framework for “cooperative analog/digital signal processing systems” is presented A key aspect of the cooperative analog/digital signal processing systems is the fact that new advances in analog VLSI circuits make it possible to developed advanced analog signal processing systems with programmable elements

Slope propagation in static timing analysis

Abstract: Static timing analysis has traditionally used the PERT method for identifying the critical path of a circuit. The authors show in this paper that due to the influence of the transition time of a signal on the subsequent path delay, the traditional timing analysis approach can report an optimistic circuit delay and may identify the wrong critical path. Also, the calculated circuit delay is a discontinuous function with respect to transistor and gate sizes, posing a severe problem for circuit optimization methods. The authors also examine an alternate approach where the propagated signal is constructed by combining the latest arrival time and the slowest transition time from all signals incident on a node. While this approach remedies the problem of discontinuity, it can significantly overestimate the circuit delay and can also identify the wrong critical path. In this paper, they therefore propose a new timing analysis algorithm and prove that it computes the correct and continuous timing graph delay and the proper critical path. The proposed algorithm selectively propagates multiple signals through each timing edge in cases where there exists ambiguity regarding which arriving signal represents the critical path. They show that the algorithm propagates the sufficient and necessary set of signals for computing the delay of a general timing graph. The authors also introduce a new property of digital gates, referred to as the transition shift property, and, using this property, show that the number of propagated signals can be significantly reduced for timing graphs of digital circuits. Finally, they discuss the computation of required times and node slacks for the traditional approaches and propose corresponding algorithms for the new approaches. They show that while the traditional approach can incur both a positive or negative error in the computed slack, the proposed algorithms compute a conservative slack for off-critical nodes and the correct and continuous slack for the critical path. The proposed algorithms were implemented in an industrial static timing analysis and optimization tool, and the authors present results for a number of industrial circuits. Their results show that the traditional timing analysis method underestimates the circuit delay by as much as 39%, while the discussed alternate approach can overestimate circuit delay by as much as 17%. The proposed method computes the correct delay, while incurring only a small run time overhead in all cases.

Self-assembling circuits with autonomous fault handling

Abstract: This paper reports on the results of our recent NASA SBIR contract, "Autonomous Self-Repairing Circuits," in which we developed a novel approach to fault-tolerant circuit synthesis utilizing a self-configurable hardware platform. The approach was based on the use of atomic components called Supercells. These Supercells perform several functions in the building of a desired target circuit: fault detection, fault isolation, configuration of new Supercells, determination of inter-cell wiring paths, and implementation of the final target circuit. By placing these tasks under the control of the Supercells themselves, the resulting system requires minimal external intervention. In particular, for a given target circuit, a fixed configuration string can be used to configure the system, regardless of the location of faults in the underlying hardware. This is because the configuration string does not directly implement the final circuit. Rather, it implements a self-organizing system, and that system then dynamically implements the desired target circuit.

Digital linearization circuit

Abstract: A solution is disclosed for achieving a functional complex base-band adaptive digital nonlinear device model providing RF-power amplifier distortion (i.e. linearization or pre-distortion) minimizing distortion characterization including memory effects. The present inventive solution is based on real device non-linear performance observations and the physical cause for the distortion is compensated in the application. This also means that a pre-distorter digital circuit is derived to have the inverse functionality of the digital device model. The model and the digital pre-distortion circuit are designed in such way, that function blocks are connected in cascade. Each function block is then designed to handle a certain type of distortion performance and can be optimized individually. The model gives possibilities to describe and evaluate different device properties. An accurate AM to AM and AM to PM characterization can be evaluated and the frequency response of the device when excited with envelope-modulated signals can be evaluated. The properties evaluated can also be used in a test procedure in a production facility to verify production quality.

TETA: transistor-level waveform evaluation for timing analysis

Abstract: Static timing analysis breaks down the longest path problem into waveform analysis of paths of logic stages that are comprised of nonlinear transistors and complex RLC loads. Runtime efficiency is of the utmost importance; however, the waveform evaluation of these logic stages cannot be accelerated via timing simulation algorithms that attempt to exploit temporal or spatial latency since the simulation problem is already a partitioned one. TETA was developed as a general purpose transistor-level waveform evaluation engine for providing accuracy-efficiency tradeoffs for these logic-stage waveform evaluation problems that are encountered during timing analysis. Of particular emphasis are the large RC(L) coupled logic stages which present the bottleneck for waveform evaluation along multiple stages of a digital circuit path. TETA applies a novel compaction scheme for the logic-stage transistor clusters and employs a novel nonlinear algebraic solution method to analyze the circuit. Importantly, stability of the waveform evaluation with TETA requires only stable single-input multi-output N-port interconnect models that are not necessarily passive. Waveform evaluators that use general transistor and piecewise linear device models require provably passive multi-input multi-output interconnect models that can be extremely inefficient for large coupled N-port problems. Furthermore, the methodology in TETA brings extra efficiency by avoiding extra matrix factorizations and enabling the use of device model tables without any loss of accuracy. Complex logic gates and nonlinear capacitors are handled without loss of generality.

A low-power adder operating on effective dynamic data ranges

Abstract: To design a power-efficient digital signal processor, this study develops a fundamental arithmetic unit of a low-power adder that operates on effective dynamic data ranges. Before performing an addition operation, the effective dynamic ranges of two input data are determined. Based on a larger effective dynamic range, only selected functional blocks of the adder are activated to generate the desired result while the input bits of the unused functional blocks remain in their previous states. The added result is then recovered to match the required word length. Using this approach to reduce switching operations of noneffective bits allows input data in 2's complement and sign magnitude representations to have similar switching activities. This investigation thus proposes a 2's complement adder with two master-stage and slave-stage flip-flops, a dynamic-range determination unit and a sign-extension unit, owing to the easy implementation of addition and subtraction in such a system. Furthermore, this adder has a minimum number of transistors addressed by carry-in bits and thus is designed to reduce the power consumption of its unused functional blocks. The dynamic range and sign-extension units are explored in detail to minimize their circuit area and power consumption. Experimental results demonstrate that the proposed 32-bit adder can reduce power dissipation of conventional low-power adders for practical multimedia applications. Besides the ripple adder, the proposed approach can be utilized in other adder cells, such as carry lookahead and carry-select adders, to compromise complexity, speed and power consumption for application-specific integrated circuits and digital signal processors.

Digital Principles and Design

Abstract: 1 Introduction2 Number Systems, Arithmetic, and Codes3 Boolean Algebra and Combinational Networks4 Simplification of Boolean Expressions5 Logic Design with MSI Components and Programmable Logic Devices6 Flip-flops and Simple Flip-flop Applications7 Synchronous Sequential Networks8 Algorithmic State Machines9 Asynchronous Sequential NetworksAppendix Digital CircuitsAppendix Altera and LogicWorks Tutorials

Multiplication logic circuit

Abstract: A multiplication logic circuit comprises array generation logic and array reduction logic. The array reduction logic comprises array reduction logic for a first level of array reduction which comprises maximal length parallel counters for reducing maximal length columns. The output of the maximal length parallel counters are then further reduced by a second level of reduction logic comprising logic circuits with asymmetric delays in order to compensate for the differential delays experienced by the outputs of the maximal length parallel counters.

Pipelined parallel processing of feedback loops in a digital circuit

Abstract: Digital circuits and methods for designing digital circuits are presented. In an embodiment, a number of bits (B) of a bit-stream to be processed in parallel by a digital circuit is selected. A clocking rate (C) is selected for the digital circuit such that a product (P), P being equal to B times C, is equal to at least 1 gigabit per second. An initial circuit capable of serially processing the bits of the bit-stream at a data processing rate less than P is formed. This initial circuit includes a feedback loop having N+1 delays. N is a whole number greater than zero. The initial circuit is unfolded by a factor of B to form B parallel processing pipelines for the bits of the bit-stream. An N-step look-ahead network is formed to provide inputs to the B parallel processing pipelines. The unfolded circuit is retimed to achieve the selected clocking rate (C).

Timing analysis of latch-controlled digital circuits with detailed clock skew analysis

Abstract: In accordance with the present invention, a method, system, computer system, and computer program product for considering clock skew in designing digital systems with latch-controlled circuits are provided. The disclosure teaches a method for determining whether logic operations can be performed within the available time and allows detailed modeling of clock skew for different domains of the integrated circuit. Taking clock skew into account for each domain, worst-case timing paths can be determined for circuits controlled by either flip-flops or latches. A design of an integrated circuit can be revised or verified using the method taught. The disclosure envisions that integrated circuits, printed circuit boards, computer systems and other components will be manufactured based upon designs developed with the method taught.

Logic characterization vehicle to determine process variation impact on yield and performance of digital circuits

Abstract: Manufacturing of integrated circuits relies on the sequence of many hundred process steps. Each of these steps will have more or less variation, which has to be within a,certain limit to guarantee the chips functionality at a target speed. But, not every chip layout is susceptive to process variation the same way, which requires a link between process,capabilities and product design. This paper will present a novel Logic Characterization Vehicle (LCV) to investigate the yield and performance impact of process variation on high volume product chips. The LCV combines and manipulates new or already documented circuits like memory cells and combinatorial logic circuits within a JIG interface that allows fast and easy testability. Beside the functionality of such circuits, also path delay as well as cross talk issues can be determined. A standard digital functional tester can be used, since all timing critical measurements will be performed within the JIG. The described method allows early implementation of existing circuits for future technology nodes (shrinks). A Design Of Experiments (DOE) based implementation of possible layout manipulations will determine their impact on yield and performance of a target design as well as its sensitivity to process variation. The described approach can be used at a much earlier stage of product and process development, which will significantly shorten yield ramp.