Showing papers on "Etching (microfabrication) published in 2007"

Method of dry etching oxide semiconductor film

Abstract: Provided is a dry etching method for an oxide semiconductor film containing at least In, Ga, and Zn, which includes etching an oxide semiconductor film in a gas atmosphere containing a halogen-based gas.

Thin film etching method

Abstract: Example methods may provide a thin film etching method. Example thin film etching methods may include forming a Ga—In—Zn—O film on a substrate, forming a mask layer covering a portion of the Ga—In—Zn—O film, and etching the Ga—In—Zn—O film using the mask layer as an etch barrier, wherein an etching gas used in the etching includes chlorine. The etching gas may further include an alkane (CnH2n+2) and H2 gas. The chlorine gas may be, for example, Cl2, BCl3, and/or CCl3, and the alkane gas may be, for example, CH4.

Dry etching method for oxide semiconductor film

Abstract: Provided is a dry etching method for an oxide semiconductor film made of In—Ga—Zn—O, in which an etching gas containing a hydrocarbon is used in a dry etching process for the oxide semiconductor film made of In—Ga—Zn—O formed on a substrate.

The effect of front ZnO:Al surface texture and optical transparency on efficient light trapping in silicon thin-film solar cells

Abstract: This study addresses the material properties of magnetron-sputtered aluminum-doped zinc oxide (ZnO:Al) films and their application as front contacts in silicon thin-film solar cells. Optimized films exhibit high conductivity and transparency, as well as a surface topography with adapted light-scattering properties to induce efficient light trapping in silicon thin-film solar cells. We investigated the influence on the ZnO:Al properties of the amount of alumina in the target as well as the substrate temperature during sputter deposition. The alumina content in the target influences the carrier concentration leading to different conductivity and free carrier absorption in the near infrared. Additionally, a distinct influence on the film growth of the ZnO:Al layer was found. The latter affects the surface topography which develops during wet-chemical etching in diluted hydrochloric acid. Depending on alumina content in the target and heater temperature, three different regimes of etching behavior have been i...

High mobility bottom gate InGaZnO thin film transistors with SiOx etch stopper

Abstract: The authors report on the fabrication of thin film transistors (TFTs), which use an amorphous indium gallium zinc oxide (a-IGZO) channel, by rf sputtering at room temperature and for which the channel length and width are patterned by photolithography and dry etching. To prevent plasma damage to the active channel, a 100-nm-thick SiOx layer deposited by plasma enhanced chemical vapor deposition was adopted as an etch stopper structure. The a-IGZO TFT (W∕L=10μm∕50μm) fabricated on glass exhibited a high field-effect mobility of 35.8cm2∕Vs, a subthreshold gate swing value of 0.59V∕decade, a thrseshold voltage of 5.9V, and an Ion∕off ratio of 4.9×106, which is acceptable for use as the switching transistor of an active-matrix TFT backplane.

Extremely high stability of glutathionate-protected Au25 clusters against core etching.

Abstract: It is well known that so-called magic-numbered clusters can be preferentially populated by dissociative excitation of larger precursors, because the energy required for removal of a single atom from a magic-numbered cluster is higher than from a neighbor. Thus, if the Au atoms can be removed sequentially from preformed thiolated-protected gold (Au:SR) clusters, one can anticipate a population growth of certain stable Aun:SR clusters. Chemical etching by free thiols is one feasible method for core size reduction of the Au:SR clusters. The etching rate of Aun:SR clusters must be determined as a function of core size, in order to provide a synthesis for welldefined Aun(SR)m clusters in large quantity, as well as to provide information regarding the stability of Aun(SR)m. In the present paper, we studied etching reactions of Aun(SG)m clusters with (n,m) = (10,10), (15,13), (18,14), (22,16), (25,18), (29,20), (33,22), (39,24) by free glutathione (GSH). It was found that Au25:SG clusters show higher stability against etching than the others and as a result two different reaction modes are operative depending on the core size. The Aun(SG)m (n < 25) clusters are completely oxidized to Au(I):SG complexes while Aun(SG)m (n ≥ 25) clusters are etched into Au25: SG by free GSH molecules. On the basis of this observation, a model is proposed to explain our recent finding that Au25 (SG)18 clusters are selectively formed during the reaction of triphenylphosphine-stabilized Au11 clusters and an excess amount of GSH.

Pitch reduced patterns relative to photolithography features

Abstract: Differently-sized features of an integrated circuit are formed by etching a substrate using a mask which is formed by combining two separately formed patterns. Pitch multiplication is used to form the relatively small features of the first pattern and conventional photolithography used to form the relatively large features of the second pattern. Pitch multiplication is accomplished by patterning a photoresist and then etching that pattern into an amorphous carbon layer. Sidewall spacers are then formed on the sidewalls of the amorphous carbon. The amorphous carbon is removed, leaving behind the sidewall spacers, which define the first mask pattern. A bottom anti-reflective coating (BARC) is then deposited around the spacers to form a planar surface and a photoresist layer is formed over the BARC. The photoresist is next patterned by conventional photolithography to form the second pattern, which is then is transferred to the BARC. The combined pattern made out by the first pattern and the second pattern is transferred to an underlying amorphous silicon layer and the pattern is subjected to a carbon strip to remove BARC and photoresist material. The combined pattern is then transferred to the silicon oxide layer and then to an amorphous carbon mask layer. The combined mask pattern, having features of difference sizes, is then etched into the underlying substrate through the amorphous carbon hard mask layer.

Ordered silicon nanowire arrays via nanosphere lithography and metal-induced etching

Abstract: Two-dimensional silica colloidal crystal template is used to create metal nanohole arrays on a silicon surface, which enables the controlled fabrication of aligned silicon nanowire (SiNW) arrays via metal catalytic etching. By varying the size of silica colloidal crystals, aligned arrays of SiNWs with desirable diameter and density could be obtained. The formation of ordered SiNW arrays is due to selective and anisotropic etching of silicon induced by the silver pattern. The orientation of SiNW arrays is influenced by silver movement in silicon, and the wire axes are primarily along the ⟨100⟩ direction.

Hierarchical silicon etched structures for controlled hydrophobicity/superhydrophobicity.

Abstract: Silicon surface hydrophobicity has been varied by using silane treatments on silicon pyramid surfaces generated by KOH anisotropic etching. Results demonstrated that by altering the surface hydrophobicity, the apparent contact angle changed in accord with the Wenzel equation for surface structures with inclined side walls. Hierarchical structures were also constructed from Si pyramids where nanostructures were added by Au-assisted electroless HF/H2O2 etching. Surface hydrophobicity and superhydrophobicity were achieved by surface modification with a variety of silanes. Stability of the Cassie state of superhydrophobicity is described with respect to the Laplace pressure as indicated by the water droplet meniscus in contact with the hierarchical structures. The contact angle hysteresis observed is also discussed with respect to water/substrate adhesion.

Solution‐Processed Full‐Color Polymer Organic Light‐Emitting Diode Displays Fabricated by Direct Photolithography

Abstract: The first full-color polymer organic light-emitting diode (OLED) display is reported, fabricated by a direct photolithography process, that is, a process that allows direct structuring of the electroluminescent layer of the OLED by exposure to UV light. The required photosensitivity is introduced by attaching oxetane side groups to the backbone of red-, green-, and blue-light-emitting polymers. This allows for the use of photolithography to selectively crosslink thin films of these polymers. Hence the solution-based process requires neither an additional etching step, as is the case for conventional photoresist lithography, nor does it rely on the use of prestructured substrates, which are required if ink-jet printing is used to pixilate the emissive layer. The process allows for low-cost display fabrication without sacrificing resolution: Structures with features in the range of 2 μm are obtained by patterning the emitting polymers via UV illumination through an ultrafine shadow mask. Compared to state-of-the-art fluorescent OLEDs, the display prototype (pixel size 200 μm × 600 μm) presented here shows very good efficiency as well as good color saturation for all three colors. The application in solid-state lighting is also possible: Pure white light [Commision Internationale de l'Eclairage (CIE) values of 0.33, 0.33 and color rendering index (CRI) of 76] is obtained at an efficiency of 5 cd A–1 by mixing the three colors in the appropriate ratio. For further enhancement of the device efficiency, an additional hole-transport layer (HTL), which is also photo-crosslinkable and therefore suitable to fabricate multilayer devices from solution, is embedded between the anode and the electroluminescent layer.

Simplified pitch doubling process flow

Abstract: A method for fabricating a semiconductor device comprises patterning a layer of photoresist material to form a plurality of mandrels. The method further comprises depositing an oxide material over the plurality of mandrels by an atomic layer deposition (ALD) process. The method further comprises anisotropically etching the oxide material from exposed horizontal surfaces. The method further comprises selectively etching photoresist material.

Convenient, Rapid Synthesis of Ag Nanowires

Abstract: The rapid, microwave-assisted aerobic synthesis of silver nanowires based on the polyol method is described. Benchtop dissolution of NaCl and AgNO3 (ratio 1:6 to 1:3) in ethylene glycol and subsequent heating using microwave irradiation (300 W) in the presence of polyvinylpyrrolidone generates Ag nanowires in ∼80% yield in 3.5 min. Upon purification, microscopy (TEM, SEM) and powder X-ray diffraction reveal a uniform set of crystalline Ag nanowires with dimensions of 45 nm × 4−12 μm. Wire formation is highly dependent upon the microwave heating power, time, and NaCl:AgNO3 ratio because of the rapid heating process and the presence of O2 as an etching coreagent. Extended microwave heating causes the wires to fuse if in proximity or degrade to shorter wires presumably via the etching reaction. In the absence of O2/Cl-, the wires melt upon extended microwave heating (>4 min), suggesting that nanowire melting may contribute to the observed morphology under etching conditions. Compared to existing wet-chemical...

Sulfur passivation for ohmic contact formation to InAs nanowires

Abstract: We have studied the formation of ohmic contacts to InAs nanowires by chemical etching and passivation of the contact areas in an ammonium polysulfide, (NH4)2Sx, water solution. The nanowires were exposed to different dilution levels of the (NH4)2Sx solution before contact metal evaporation. A process based on a highly diluted (NH4)2Sx solution was found to be self-terminating, with minimal etching of the InAs. The stability of the contacts was investigated with electrical measurements as a function of storage time in vacuum and air.

Preparation, Structure, and Optical Properties of Nanoporous Gold Thin Films

Abstract: Thin nanoporous gold (np-Au) films, ranging in thickness from ∼40 to 1600 nm, have been prepared by selective chemical etching of Ag from Ag/Au alloy films supported on planar substrates. A combination of scanning electron microscopy (SEM) imaging, synchrotron grazing incidence small angle X-ray scattering, and N2 adsorption surface area measurements shows the films to exhibit a porous structure with intertwined gold fibrils exhibiting a spectrum of feature sizes and spacings ranging from several to hundreds of nanometers. Spectroscopic ellipsometry measurements (300−800 nm) reveal the onset of surface plasmon types of features with increase of film thicknesses into the ∼200 nm film thickness range. Raman scattering measurements for films functionalized with a self-assembled monolayer formed from 4-fluorobenzenethiol show significant enhancements which vary sharply with film thickness and etching times. The maximum enhancement factors reach ∼104 for 632.8 nm excitation, peak sharply in the ∼200 nm thickne...

ZnO thin films and light-emitting diodes

Abstract: ZnO is attracting considerable attention for its possible application to light-emitting sources due to its advantages over GaN. We review the recent progress in the growth of ZnO epitaxial films, doping control, device fabrication processes including etching and ohmic contact formation, and finally the prospects for fabrication and characteristics of ZnO light-emitting diodes.

Improved External Extraction Light Emitting Diode based upon Crystallographic Faceted Surfaces

Abstract: A light emitting diode is disclosed that includes a support structure and a Group III nitride light emitting active structure mesa on the support structure. The mesa has its sidewalls along an indexed crystal plane of the Group III nitride. A method of forming the diode is also disclosed that includes the steps of removing a substrate from a Group III nitride light emitting structure that includes a sub-mount structure on the Group III nitride light emitting structure opposite the substrate, and thereafter etching the surface of the Group III nitride from which the substrate has been removed with an anisotropic etch to develop crystal facets on the surface in which the facets are along an index plane of the Group III nitride. The method can also include etching the light emitting structure with an anisotropic etch to form a mesa with edges along an index plane of the Group III nitride.

Inverse slope isolation and dual surface orientation integration

Abstract: A semiconductor process and apparatus provide a high performance CMOS devices (108, 109) with hybrid or dual substrates by etching a deposited oxide layer (62) using inverse slope isolation techniques to form tapered isolation regions (76) and expose underlying semiconductor layers (41, 42) in a bulk wafer structure prior to epitaxially growing the first and second substrates (84, 82) having different surface orientations that may be planarized with a single CMP process. By forming first gate electrodes (104) over a first substrate (84) that is formed by epitaxially growing (100) silicon and forming second gate electrodes (103) over a second substrate (82) that is formed by epitaxially growing (110) silicon, a high performance CMOS device is obtained which includes high-k metal PMOS gate electrodes having improved hole mobility.

Modulating etch selectivity and etch rate of silicon nitride thin films

Abstract: Etching of nitride and oxide layers with reactant gases is modulated by etching in different process regimes. High etch selectivity to silicon nitride is achieved in an adsorption regime where the partial pressure of the etchant is lower than its vapor pressure. Low etch selectivity to silicon nitride is achieved in a condensation regime where the partial pressure of the etchant is higher than its vapor pressure. By controlling partial pressure of the etchant, very high etch selectivity to silicon nitride may be achieved.

Shallow trench isolation using atomic layer deposition during fabrication of a semiconductor device

Abstract: A method for providing an isolation material, for example trench isolation for a semiconductor device, comprises forming a first dielectric such as silicon dioxide using an atomic layer deposition (ALD) process within a trench, partially etching the first dielectric, then forming a second dielectric such as a silicon dioxide using a high density plasma (HDP) deposition within the trench. The second dielectric provides desirable properties such as resistance to specific etches than the first dielectric, while the first dielectric fills high aspect ratio openings more easily than the second dielectric. Depositing the first dielectric results in a decreased trench aspect ratio which must be filled by the second dielectric.

Method, system, and apparatus for the growth of SiC and related or similar material, by chemical vapor deposition, using precursors in modified cold-wall reactor

Abstract: An approach for the growth of high-quality epitaxial silicon carbide (SiC) films and boules, using the Chemical Vapor Deposition (CVD) technique is described here. The method comprises modifications in the design of the typical cold-wall CVD reactors, providing a better temperature uniformity in the reactor bulk and a low temperature gradient in the vicinity of the substrate, and an approach to increase the silicon carbide growth rate and to improve the quality of the growing layers, using halogenated carbon-containing precursors (carbon tetrachloride CCl 4 or halogenated hydrocarbons, CHCl 3 , CH 2 Cl 2 , CH 3 Cl, etc.), or introducing other chlorine-containing species in the gas phase in the growth chamber. The etching effect, proper ranges, and high temperature growth are also examined.

Etching of nano-imprint templates using an etch reactor

Abstract: Methods for etching a metal layer using an imprinted resist material are provided. In one embodiment, a method for processing a photolithographic reticle includes providing a reticle having a metal photomask layer formed on an optically transparent substrate and an imprinted resist material deposited on the metal photomask layer, etching recessed regions of the imprinted resist material to expose portions of the metal photomask layer in a first etching step, and etching the exposed portions of the metal photomask layer through the imprinted resist material in a second etching step, wherein at least one of the first or second etching steps utilizes a plasma formed from a processing gas comprising oxygen, halogen and chlorine containing gases. In one embodiment, the process gas is utilized in both the first and second etching steps. In another embodiment, the first and second etching steps are performed in the same processing chamber.

Nanotextured super-hydrophobic transparent poly(methyl methacrylate) surfaces using high-density plasma processing

Abstract: We present an environmentally friendly, rapid, no-rinse and mass-production amenable plasma process for the fabrication of super-hydrophobic (SH) poly(methyl methacrylate) (PMMA) surfaces using only a one load/unload step in a low-pressure, high-density plasma reactor. First, oxygen plasma is applied to nanotexture the PMMA surface via etching processes leading to high aspect ratio (HAR) topography, with dual-roughness characteristics for short process durations, as evidenced by AFM analysis. The duration of the process may range from 1 min to several min depending on the roughness amplitude and on the degree of transparency desired. The significance of the ion-bombardment is revealed and discussed. After this first step, the gas chemistry is changed to a fluorocarbon one which leads to a few nanometres-thick Teflon-like film deposition, thus altering the PMMA surface chemistry within a few seconds. Following this process, a very large area (depending on the reactor scale) of the PMMA may become SH in less than 1.5 min (total process duration) with a transparency as desired (from fully transparent to milky and antireflective). The contact angles (CA) measured are approximately 152° with 5° hysteresis. For short process durations, the dual-roughness character of PMMA surfaces favours the SH formation, despite the low roughness factor. Furthermore, the dry and low-temperature character of the process ensures the intactness of PMMA's shape and bulk mechanical properties.

Comparison of atomic scale etching of poly-Si in inductively coupled Ar and He plasmas

Abstract: Atomic scale etching (ASE) of poly-Si, which can give etching with atomic scale accuracy, was investigated in inductively coupled Ar and He plasmas. ASE used a cyclic operation of gas adsorption and ion beam irradiation, which is the same concept as atomic layer etching of single crystal substrates. The etch rate gradually increased, reached the saturated region, and then rapidly increased with increasing bias voltage (or ion energy) in both Ar and He plasmas. This saturation region offered a process window for the realization of ASE. At the bias voltage within the process window for ASE, the etch rate was self-limited with respect to the duration of ion beam irradiation for both Ar and He plasmas, confirming that ASE of poly-Si was successfully achieved in both Ar and He plasmas. The range of the process window for ASE using He plasmas was about 10 times wider than that using Ar plasmas. This is because heavier Ar ions impart a greater fraction of ion energy to the surface atoms compared to lighter He ions.

Templated fabrication of large area subwavelength antireflection gratings on silicon

Abstract: We report a cheap and scalable bottom-up technique for fabricating wafer-scale, subwavelength-structured antireflection coatings on single-crystalline silicon substrates. Spin-coated monolayer colloidal crystals are utilized as shadow masks to generate metallic nanohole arrays. Inverted pyramid arrays in silicon can then be templated against nanoholes by anisotropic wet etching. The resulting subwavelength gratings greatly suppress specular reflection at normal incidence. The reflection spectra for flat silicon and the templated gratings at long wavelengths agree well with the simulated results using a rigorous coupled wave analysis model. These subwavelength gratings are of great technological importance in crystalline silicon solar cells.

Fabrication of low-loss channel waveguides in Al2O3 and Y2O3 layers by inductively coupled plasma reactive ion etching

Abstract: Etching of amorphous Al2O3 and polycrystalline Y2O3 films has been investigated using an inductively coupled reactive ion etch system. The etch behaviour has been studied by applying various common process gases and combinations of these gases, including CF4/O2, BCl3, BCl3/HBr, Cl2, Cl2/Ar and Ar. The observed etch rates of Al2O3 films were much higher than Y2O3 for all process gases except for Ar, indicating a much stronger chemical etching component for the Al2O3 layers. Based on analysis of the film etch rates and an investigation of the selectivity and patterning feasibility of possible mask materials, optimized optical channel-waveguide structures were fabricated in both materials. In Al2O3, channel waveguides were fabricated with BCl3/HBr plasma and using a standard resist mask, while in Y2O3, channel waveguides were fabricated with Ar and using either a resist or a sputter deposited Al2O3 mask layer. The etched structures in both materials exhibit straight sidewalls with minimal roughness and sufficient etch depths (up to 530 nm for Al2O3 and 250 nm for Y2O3) for defining waveguides with strong optical confinement. Using the developed etch processes, low additional optical propagation losses (on the order of 0.1 dB/cm) were demonstrated in single-mode ridge waveguides in both Al2O3 and Y2O3 layers at 1550 nm.

AlGaN/GaN HEMTs With Thin InGaN Cap Layer for Normally Off Operation

Abstract: AlGaN/GaN HEMTs with a thin InGaN cap layer have been proposed to implement the normally off HEMTs. The key idea is to employ the polarization-induced field in the InGaN cap layer, by which the conduction band is raised, which leads to the normally off operation. The fabricated HEMT with an In0.2Ga0.8N cap layer with a thickness of 5 nm showed normally off operation with a threshold voltage of 0.4 V and a maximum transconductance of 85 mS/mm for the device with a 1.9-mum-long gate. By etching off the In0.2Ga0.8N cap layer at the access region using gate electrode as an etching mask, the maximum transconductance has increased from 85 to 130 mS/mm due to a reduction of the parasitic source resistance.

Method of forming fine patterns of semiconductor device using double patterning

Abstract: A method of forming fine patterns of a semiconductor device includes double etching by changing a quantity of producing polymer by-products to etch a film with different thicknesses in regions having different pattern densities. In a first etching, reactive ion etching (RIE) is performed upon a buffer layer and a hardmask layer both in a low-density pattern region and a high-density pattern region under a first etching ambient until an etch film is exposed in the low-density pattern region using mask patterns as an etch mask. In second etching for forming the hardmask patterns, using the mask patterns as an etch mask, the hardmask layer is etched until the etch film is exposed in the high-density pattern region while accumulating polymer by-products on the etch film in the low-density pattern region under a second etching ambient having polymer by-products produced greater than in the first etching ambient.

Nano-fabrication with metallic glass-an exotic material for nano-electromechanical systems.

Abstract: Completely glassy thin films of Zr-Al-Cu-Ni exhibiting a large supercooled liquid region (DeltaT(x) = 95 K), very smooth surface (R(a) = 0.2 nm) and high value of Vickers hardness (H(v) = 940) were deposited by sputtering. The micro/nano-patterning ability of these films is demonstrated by focused ion beam etching (smallest pattern approximately 12 nm), as well as by the imprint lithography technique (smallest feature approximately 34 nm). These glassy films having very good mechanical and chemical properties, combined with superb nano-patterning ability, integrateable with silicon integrated circuit technology, are promising for fabrication of a wide range of two- or three-dimensional components for future nano-electromechanical systems.