Showing papers on "Mixed-signal integrated circuit published in 1995"

CMOS Digital Integrated Circuits Analysis & Design

Abstract: CMOS Digital Integrated Circuits: Analysis and Design is the most complete book on the market for CMOS circuits. Appropriate for electrical engineering and computer science, this book starts with CMOS processing, and then covers MOS transistor models, basic CMOS gates, interconnect effects, dynamic circuits, memory circuits, BiCMOS circuits, I/O circuits, VLSI design methodologies, low-power design techniques, design for manufacturability and design for testability. This book provides rigorous treatment of basic design concepts with detailed examples. It typically addresses both the computer-aided analysis issues and the design issues for most of the circuit examples. Numerous SPICE simulation results are also provided for illustration of basic concepts. Through rigorous analysis of CMOS circuits in this text, students will be able to learn the fundamentals of CMOS VLSI design, which is the driving force behind the development of advanced computer hardware. Table of contents 1 Introduction 2 Fabrication of MOSFETS 3 MOS Transistor 4 Modeling of MOS Transistors Using SPICE 5 MOS Inverters: Static Characteristics 6 MOS Inverters: Switching Characteristics and Interconnect Effects 7 Combinational MOS Logic Circuits 8 Sequential MOS Logic Circuits 9 Dynamic Logic Circuits 10 Semiconductor Memories 11 Low-Power CMOS Logic Circuits 12 BiCMOS Logic Circuits 13 Chip Input and Output (I/O) Circuits 14 Design for Manufacturability 15 Design for Testability

A 70-MS/s 110-mW 8-b CMOS folding and interpolating A/D converter

Abstract: A CMOS analog to digital converter based on the folding and interpolating technique is presented. This technique is successfully applied in bipolar A/D converters and now also becomes available in CMOS technology. The analog bandwidth of the A/D converter is increased by using a transresistance amplifier at the outputs of the folding amplifiers and, due to careful circuit design, the comparators need no offset compensation. The result is a small area (0.7 mm/sup 2/ in 0.8 /spl mu/m CMOS), high speed (70 MS/s), and low-power (110 mW at 5 V supply, including reference ladder) A/D converter. A 3.3 V supply version of the circuit runs at 45 MS/s and dissipates 45 mW.

Modeling and analysis of substrate coupling in integrated circuits

Abstract: A technique is presented for efficient calculation of substrate macromodels, which can be used to determine substrate coupling in integrated circuits. Examples of the technique applied to several test structures are presented.

Extraction of circuit models for substrate cross-talk

Abstract: An increasingly urgent topic for the realization of densely packed (mixed signal) integrated circuits is prevention of cross-talk via the substrate. This paper proposes a Boundary Element Method (BEM) for calculating an admittance matrix for the substrate in order to analyze the parasitic coupling during layout verification.In contrast with standard BE methods, we propose a Green's function which is specific to the domain and the problem. This allows minimal discretization and a direct extraction of circuit models for the cross-talk. The extraction can be combined with an efficient model reduction technique to obtain more simple, yet accurate models for the cross-talk. The complete extraction process has a linear time complexity and a constant memory usage. The method is fully implemented and integrated in an existing layout-to-circuit extractor.

A transconductor-based field-programmable analog array

Abstract: Field-programmable gate arrays for prototyping digital circuits are a widely endorsed approach for reducing time-to-market. Offering similar advantages, a field-programmable analog array (FPAA) for prototyping continuous-time analog circuits is reported here. Conceptually, a FPAA consists of configurable analog blocks (CABs) and interconnects. The function of each CAB and the connections among CABs are determined by the contents of an on-chip shift register. Different circuits can be instantiated using a FPAA by loading in different configuration bits. This IC strategy offers simplified analog circuit design with the advantages of instant prototyping, programmable topology, programmable parameters, CAD compatibility, and testability.

Programming programmable transistor devices using state machines

Abstract: An integrated circuit with programmable transistors is programmed via a state machine on the integrated circuit For example, the integrated circuit may be a programmable logic device, and the state machine may be a JTAG state machine Each integrated circuit may have on it a register containing data indicating how long a particular programming operation should continue in order to be successful for that circuit External programming control apparatus first reads that data and then at least partly bases the timing of programming instructions applied to the integrated circuit on that data The integrated circuit may have an on-board programming voltage generating circuit which is turned on only by appropriate instructions from the external programming control apparatus The external programming control apparatus controls the sequence and timing of all programming operations via the state machine port of the integrated circuit

Analog IC design automation. I. Automated circuit generation: new concepts and methods

Abstract: The research presented in this paper is concerned with the automation of analog integrated circuit design and, in particular, with a description of methods and techniques employed by the ISAID design system developed at Imperial College, UK. ISAID is comprised of two modules: the circuit generator and the circuit corrector. The circuit generator is based on newly developed methods that are used to handle hierarchical generation of topologies and size MOS transistors so that the performance of designed circuits compare satisfactorily with their specifications. To avoid long design times, simulation is used only after the generation of an initial circuit topology. Simulated performances may therefore be found to differ from the required. One novel feature of the proposed methodology is that in such cases a circuit corrector is invoked to correct the initial design. The circuit corrector is essentially a novel application of qualitative reasoning, which, without iterative simulation analyses performance trade-offs, thereby selects circuit adjustments-transistor size adjustments or topological modifications-that would improve the problematic performances. Several design examples have demonstrated the benefits of the ISAID design approach. >

Addressing noise decoupling in mixed-signal IC's: power distribution design and cell customization

Abstract: An important and largely unexplored aspect of power distribution synthesis is cell customization. Through automatic cell customization, power I/O cell assignments and local substrate and power supply decoupling may be tailored to reduce deleterious noise effects on analog circuits in mixed-signal environments. Techniques for simultaneous power grid design (topology and sizing) and cell configuration/customization are described that allow designers to handle more difficult chip-level noise problems. Synthesis results on an industrial mixed-signal example demonstrate the effectiveness of this approach. >

Analog Signal Generation for Built-In-Self-Test of Mixed-Signal Integrated Circuits

Abstract: Preface. 1. Introduction. 2. An Oversampling-Based Analog Oscillator. 3. Analog Multi-Tone Signal Generation. 4. An Oversampling-Based Function Generator. 5. Conclusion. A: Delta-Sigma Modulation. B: VHDL Description: Single-Tone Oscillator. C: Verilog Description: Single-Tone Oscillator. D: HSPICE Reconstruction Program. References. Index.

Substrate-aware mixed-signal macrocell placement in WRIGHT

Abstract: We describe a set of placement algorithms for handling substrate coupled switching noise. A typical mixed-signal IC has both sensitive analog and noisy digital circuits, and the common substrate parasitically couples digital switching transients into the sensitive analog regions of the chip. To preserve the integrity of sensitive analog signals, it is thus necessary to electrically isolate the analog and digital. We argue that optimal area utilization requires such isolation be designed into the system during first-cut chip-level placement. We present algorithms that incorporate commonly used isolation techniques within an automatic placement framework. Our substrate-noise evaluation mechanism uses a simplified substrate model and simple electrical representations for the noisy digital macrocells. The digital/analog interactions determined through these models are incorporated into a simulated annealing macrocell placement framework. Automatic placement results indicate these substrate-aware algorithms allow efficient mixed-signal placement optimization. >

Analog to digital and digital to analog conversion based on stochastic logic

Abstract: Digital to analog and analog to digital conversions can be realized in VLSI integrated circuits using a strictly digital technology and some additional analog circuits outside the IC. These techniques are based on the generation of a pulse sequence that represents a digital number. The mean value of this pulse sequence is obtained at the output of a low-pass external filter. The authors propose the use a stochastic pulse sequence instead of a traditional PWM signal. This technique has important advantages. Stochastic pulse sequences can be mathematically processed by extremely simple circuits. The product and addition of stochastic pulses can be evaluated by AND gates. The spectral properties of stochastic pulse sequences lead to less restrictive conditions to be imposed to the filter that makes the analog conversion of the pulse sequence. The authors have used this technique to implement digital to analog and analog to digital conversion in an integrated circuit that is currently being designed for a Spanish company.

Semiconductor integrated circuit for developing a system using a microprocessor

Abstract: An application system using a large scale semiconductor integrated circuit is provided with a connection. A programmable semiconductor integrated circuit is connected to the application system via the connection and an input/output terminal of the programmable semiconductor integrated circuit. The programmable semiconductor integrated circuit is provided with a microprocessor connector, to which a probe of an ICE is connected. The programmable semiconductor integrated circuit functions as a peripheral circuit contained in the large scale semiconductor integrated circuit, so that the conventional ICE can be used.

An InP-based HBT fab for high-speed digital, analog, mixed-signal, and optoelectronic ICs

Abstract: Integrated circuits (ICs) utilizing indium phosphide based heterojunction bipolar transistors (HBTs) have set numerous speed and bandwidth records over the past several years This paper describes the extension of that HBT IC technology to an IC fabrication capability which is quite versatile in being able to produce digital, analog, mixed signal, and optoelectronic ICs within the same process This enables the fab line to quickly respond to varying demands Three ICs are discussed which exemplify the capability of this fab: (1) a 7 GHz 12-bit accumulator; (2) a nearly ideal continuous-time-sampling second-order /spl Delta//spl Sigma/ modulator operating at a 32 GHz sample rate; and (3) a monolithic 4-channel optoelectronic receiver array capable of 20 Gb/s operation

A programmable input/output driver circuit capable of operating at a variety of voltage levels and having a programmable pull up/pull down function

Abstract: An integrated circuit is presented having a driver circuit programmable to produce a variety of output voltages and conductive to the voltage levels of circuits interfaced by the integrated circuit. The integrated circuit includes programmable pull up and pull down functions. The integrated circuit may be configured into an application having devices powered by a power supply voltage which is substantially larger than the voltage supplying the core section of the integrated circuit. Additionally, the present integrated circuit may be configured into other applications having devices powered by a power supply voltage substantially similar to the voltage supplying the integrated circuit core section. The present integrated circuit therefore retains utility for a large variety of applications. The pull up and pull down transistors may be programmed to provide a resistive one, resistive zero, or neither.

Integrated circuit design and manufacturing method and an apparatus for designing an integrated circuit in accordance with the method

Abstract: A method for designing an integrated circuit involves a four step process. First, a behavioral circuit model (BCM) is read which contains assignment statements which identify the logical operation of an integrated circuit (IC). The BCM is translated to a data file which described a plurality of interconnected logic gate functions to duplicate the operation of the BCM. The gates in the data file are then assigned a specific Vdd and ground rail size, a specific drive strength for speed considerations, and a cell pitch or height to optimize physical layout, in any order. The result in a physical design file which may be used to form masks and integrated circuits having optimized speed and optimized circuit area in a short design cycle.

Vertical signal transmission in three-dimensional integrated circuits by capacitive coupling

Abstract: In this paper, methods for direct vertical transmission of digital signals between adjacent chiplayers in three-dimensional circuit structures are presented. Alternative circuit schemes are investigated and compared to state-of-the-art structures with respect to signal delay and power dissipation. Improvements of over 30% in terms of speed and up to an order of magnitude in terms of dynamic power dissipation are achievable. Analytical calculations, simulations and experimental results show the suitability of the architectures for vertical signal transmission of high bandwidth digital information.

A 1 V CMOS op amp using bulk-driven MOSFETs

Abstract: It is important to develop circuit techniques that permit existing CMOS to implement analog circuits at power supply voltages as low as 1 V. This paper describes some of these techniques and illustrates their application in the design of a CMOS op amp operating from a 1 V power supply. This opamp uses a digital 2-/spl mu/m CMOS having threshold voltages of 0.7 to 0.8 V and demonstrates performance comparable with opamps using higher power supply voltages.

Pseudo-random testing and signature analysis for mixed-signal circuits

Abstract: In this paper, we address the problem of functional testing of mixed-signal circuits using pseudo-random patterns. By embedding the linear, time-invariant (LTI) analog circuit between a digital-to-analog converter (DAC) and an analog-to-digital converter (ADC), we can model the analog and converter circuitry as a digital LTI system and test it using the pseudo-random vectors. We give mathematical analysis and formulate the pseudo-random testing process as the linear transformation of a random process by the analog LTI device under test (DUT). We choose the first and the second moments of the transformed random process, which are closely related to the functionality of the DUT, as the signatures for fault detection. We show that such signatures can be estimated by proper arithmetic operations on the output responses of the DUT to the vectors generated by LFSRs. We illustrate and compare the effectiveness of several possible choices of signatures, through analysis and experimental results of several circuits, in terms of their fault detection capabilities and the testing hardware requirements.

Circuitry for allowing two drivers to communicate with two receivers using one transmission line

Abstract: The present invention allows for the simultaneous transmission of two digital signals from one integrated circuit to another. The two digital signals are encoded utilizing a voltage divider circuit and are then transmitted by one transmission line to the second integrated circuit chip. The second integrated circuit chip decodes the first digital signal and then utilizes this decoded digital signal to further decode the second digital signal.

Fast parasitic extraction for substrate coupling in mixed-signal ICs

Abstract: Techniques for the fast extraction of substrate resistances in mixed-signal integrated circuits are presented. For a given process, a simple analytical model for point-to-point substrate impedance is determined during a preprocessing stage. A hierarchical extraction strategy is then employed using this simple analytical model in conjunction with a delimitation technique to quickly determine resistive coupling through the substrate on a cell-by-cell basis. The extraction procedure yields a resistive netlist which when simulated along with necessary parasitic capacitances and the circuit itself determines any performance limitations in the design due to substrate coupling. The extraction procedure has been used in the verification and redesign of a triple 8-bit video A/D converter IC for substrate-noise problems.

Defect-oriented test methodology for complex mixed-signal circuits

Abstract: Testing of analog blocks in digital circuits is emerging as a critical factor in the success of mixed-signal ICs. The present specification-oriented testing of these blocks results in high test costs and doesn't ensure detection of all defects, causing potential reliability problems. To solve these problems, in this paper a defect-oriented test methodology for mixed analog-digital circuits is proposed. The strength of the method is demonstrated by an implementation for a complex mixed-signal circuit, a flash analog-to-digital converter. It is shown that with simple tests 93% of the defects in this circuit can be detected. Moreover application of DfT guidelines derived from this test methodology may improve the defect coverage to 99%. First impressions lead to the conclusion that the analyzed test obtains a higher defect coverage with lower test costs than functional tests. >

Analog checkers with absolute and relative tolerances

Abstract: The design of checkers aimed at the concurrent test of analog and mixed-signal circuits is considered in this paper. These checkers can on-line test duplicated and fully differential analog circuits. The test approach is based on exploiting the inherent redundancy of these circuits which results in the use of a code for the analog signals. The analog code is monitored by the checkers. An error signal which complies with existing digital self-checking parts is generated in the case that a code fails out of the valid code space. For the verification of the analog codes, absolute tolerance margins and tolerance margins which are made relative to signal amplitude are considered. A test pattern generator for off-line testing of the checkers is proposed. >

High-Frequency Analog Integrated Circuit Design

Abstract: Integrated Circuit Processing Technology MESFET Design and Modelling Schottky Diode and Passive Components Basic Building Blocks Wideband Amplifiers Operational Amplifiers Mixers and Oscillators Data Conversion Circuits Synthesis of Linearized Conductance Functions.

Mixed-Signal Switching Noise Analysis Using Voronoi-Tessellated Substrate Macromodels

Abstract: We present a new modeling technique for analyzing the impact of substrate-coupled switching noise in CMOS mixed-signal circuits. Lumped element RC substrate macromodels are efficiently generated from layout using Voronoi tessellation. The models retain the accuracy of previously proposed models, but contain orders of magnitude fewer circuit nodes, and are suitable for analyzing large-scale circuits. The modeling strategy has been verified using detailed device simulation, and applied to some mixed-A/D circuit examples.

A 200 mm SiGe-HBT BiCMOS technology for mixed signal applications

Abstract: A BiCMOS technology including 0.25 /spl mu/m electrical channel length (L/sub EFF/) nFET and pFET CMOS devices and 60 GHz f/sub max/ SiGe-HBT transistors has been achieved on 200 mm wafers. Both CMOS circuits and SiGe-HBT analog circuits were fabricated on the same chip to demonstrate the high integration capabilities of the technology. The CMOS circuits include CMOS ring oscillators and a 64 k SRAM with a 34 /spl mu/m/sup 2/ cell size. The SiGe-HBT circuits include ECL ring oscillators and a Voltage Controlled Oscillator (VCO). This is the highest level of integration yet achieved for any SiGe-base bipolar technology.

Noise reduction in integrated circuits and circuit assemblies

Abstract: The present invention encompasses techniques for reducing digital noise in integrated circuits and circuit assemblies, particularly dense mixed-signal integrated circuits, based upon shaping the noise from the digital circuit and concentrating it in a single, or a small number, of parts of the frequency spectrum. Generally, the presence of noise in the analog circuit is less important at certain frequencies, and therefore the spectral peak or peaks from the digital circuit can be carefully placed to result in little or no interference. As an example, a radio receiver might be designed such that the peaks of the digital noise lie between received channels, outside the band edges of each.

Verification of transient response of linear analog circuits

Abstract: With the introduction of complex analog designs the need to verify the circuit behavior completely and efficiently cannot be overemphasized. Recognizing the limitation of circuit simulation to achieve this goal, we present a novel approach based on formal techniques developed for digital circuits. Given a transfer function (specification) and its implementation using operational amplifier macro circuits, we verify the correctness of the transient behavior of the implementation over all possible input waveforms. Transforming the specification and the extracted state equations of the implementation from the s-domain to the Z-domain facilitates a digital representation in terms of adders, multipliers and delay elements. These two digitized circuits are then compared using techniques for checking compatibility of states in finite state machines. An example that illustrates the technique is presented.

A new symbolic program package for the interactive design of analog circuits

Abstract: A new program package which constitutes an environment for the interactive exploration and improvement of analog circuit topologies is presented in this paper. The environment is provided with functionalities which permit the graphical schematic entry of the circuit, the symbolic analysis, the approximation of the symbolic results, the use of an external numerical simulator and the graphical postprocessing of both the symbolic and numerical simulation results. These functionalities allow us to immediately evaluate the influence of both topology and component value changes on the circuit behavior. The result is useful for educational/training purposes and for the interactive synthesis of new high-performance analog circuits.