Showing papers on "Operational amplifier published in 2021"
TL;DR: An accurate current-mode bandgap reference circuit design with a novel shared offset compensation scheme for its internal amplifiers that allows to conserve die size and power consumption by preventing that each amplifier is accompanied by its own active auxiliary offset-cancellation circuit.
Abstract: This article introduces an accurate current-mode bandgap reference circuit design with a novel shared offset compensation scheme for its internal amplifiers. This bandgap circuit has been designed to operate over a very wide temperature range from −40 °C to 150 °C. Its output voltage is 1.16 V with a 3.3-V supply voltage. A multi-section curvature compensation method alleviates the error from the bipolar junction transistor’s base–emitter nonlinear voltage dependence on temperature. The bandgap reference circuit contains two operational amplifiers that are utilized to generate proportional-to-absolute-temperature (PTAT) and complementary-to-absolute-temperature (CTAT) current sources. With the implementation of the described shared offset-cancellation methodology, the simulated output inaccuracy introduced by the amplifier is kept to a 5 $\sigma $ offset within ±4.6 $\mu \text{V}$ while allowing to conserve die size and power consumption by preventing that each amplifier is accompanied by its own active auxiliary offset-cancellation circuit. Designed and fabricated in a 130-nm CMOS process technology, the bandgap reference has a measured output voltage shift of less than 1 mV over a −40 °C to 150 °C temperature range and an overall variation of ±8.2 mV across seven measured samples without trimming.
32 citations
TL;DR: In this article, an inverter-based, fully differential, body-driven, rail-to-rail, input stage topology is proposed, where the input stage exploits a replica bias control loop to set the common mode current and a common mode feed-forward strategy to set its output common mode voltage.
Abstract: A novel, inverter-based, fully differential, body-driven, rail-to-rail, input stage topology is proposed in this paper. The input stage exploits a replica bias control loop to set the common mode current and a common mode feed-forward strategy to set its output common mode voltage. This novel cell is used to build an ultralow voltage (ULV), ultralow-power (ULP), two-stage, unbuffered operational amplifier. A dual path compensation strategy is exploited to improve the frequency response of the circuit. The amplifier has been designed in a commercial 130 nm CMOS technology from STMicroelectronics and is able to operate with a nominal supply voltage of 0.3 V and a power consumption as low as 11.4 nW, while showing about 65 dB gain, a gain bandwidth product around 3.6 kHz with a 50 pF load capacitance and a common mode rejection ratio (CMRR) in excess of 60 dB. Transistor-level simulations show that the proposed circuit outperforms most of the state of the art amplifiers in terms of the main figures of merit. The results of extensive parametric and Monte Carlo simulations have demonstrated the robustness of the proposed circuit to PVT and mismatch variations.
22 citations
TL;DR: In this paper, a 16-channel neural analog-to-digital converter (ADC) is proposed, which employs a dynamic differential-difference comparator architecture with a super-GϵOmega$ input impedance ensuring negligible gate-leakage current and well-matched differential inputs.
Abstract: The presented 16-channel $\Delta $ -modulated neural analog-to-digital converter (ADC) exhibits tolerance to input dc offsets of any value, up to the supply voltage. It employs a dynamic differential-difference comparator architecture with a super- $\text{G}\Omega $ input impedance ensuring negligible gate-leakage current and well-matched differential inputs resulting in more than 78 dB of rejection of common-mode signals and artifacts. The all-digital nature of the presented $\Delta $ -ADC enables sampling of input signals at high oversampling ratios (OSRs) making the front-end immune to stimulation artifacts with differential amplitudes up to a limit that is scalable by the OSR (e.g., 10 mVPP at OSR $=\,\,10$ k). Moreover, it allows the $\Delta $ -ADC to linearly scale down the power consumption required by the application’s recording bandwidth. The oversampled $\Delta $ -ADC achieves an effective number of bits (ENOB) of 9.7-bit and 2.6- $\mu \text{V}_{\mathrm {RMS}}$ integrated input-referred noise over 1 Hz to 500-Hz bandwidth. It uses no large passives or statically biased circuits, such as operational amplifiers (Opamps) saving both channel area (0.011 mm2) and power consumption (0.99 $\mu \text{W}$ ). Experimentally measured results validate the key features of the design and include in vivo recordings in freely moving guinea pigs. The fabricated prototype system-on-a-chip (SoC) hosts an array of 16-channel neural-ADC with in-channel digitally programmable high-compliance current-mode biphasic stimulators as well as wireless circuitry for data communication and power/command reception.
21 citations
TL;DR: The enhanced topology is merged with a conventional bulk-driven input differential pair using cross-coupled connections to significantly increase the transconductance and lead to an improvement in the amplifier’s specifications, such as dc gain, slew rate, and input noise without any degeneration in other parameters.
Abstract: This article presents a low-voltage high-transconductance input differential pair for bulk-driven amplifiers. The proposed structure employs two bulk-driven flipped voltage follower (FVF) cells as nonlinear tail current sources to enhance the slewing behavior. This method also increases the transconductance of the proposed amplifier two times against the conventional one. The enhanced topology is merged with a conventional bulk-driven input differential pair using cross-coupled connections to significantly increase the transconductance. These circuitry ideas lead to an improvement in the amplifier’s specifications, such as dc gain, slew rate (SR), and input noise without any degeneration in other parameters. Moreover, thanks to the use of the bulk terminals as the input nodes and also a simple common-source structure as the second stage, rail-to-rail input, and output swings are achieved, respectively. The proposed amplifier was fabricated in TSMC 0.18- $\mu \text{m}$ CMOS technology. Under a supply voltage of 0.5 V, the measurement results show that the proposed amplifier achieves a dc gain of 78 dB, a gain bandwidth of 7.5 kHz, and an SR of 8.6 V/ms with just 91-nA current dissipation.
21 citations
TL;DR: In this article, a low unity gain frequency and low power consumption instrumentation amplifier (UGFPCIA) was designed and applied to the readout circuit of the potentiometric biosensor measurement system.
Abstract: In this study, a novel low unity-gain frequency and low power consumption instrumentation amplifier (UGFPCIA) was designed and applied to the readout circuit of the potentiometric biosensor measurement system. The proposed UGFPCIA was developed using the Taiwan Semiconductor Manufacturing Company (TSMC) 0.18- $\mu \text{m}$ process technology, and simulated in a Laker analog design environment, and had a 1.5-V supply voltage for reduced power consumption. The uric acid (UA) biosensor based on RuO2 thin film was fabricated in this study. The sensing characteristics of the RuO2 UA biosensor were measured by the proposed UGFPCIA and the LT1167, a commercial instrumentation amplifier; then, their readout circuits were compared. According to the chip measurement results, the proposed UGFPCIA achieved a common-mode gain of −54 dB and a unity-gain frequency (UGF) of 588 kHz. Its power consumption was $397.92~\mu \text{W}$ . Moreover, the measurement results showed that the sensitivity and linearity of the flexible arrayed RuO2 UA biosensor were 7.15 mV/(mg/dL) and 0.997, respectively. The LT1167 used a 2.3-V minimum supply voltage, while the proposed UGFPCIA used a 1.5-V minimum supply voltage; the power consumption is 84% lower than the former. This indicates that UGFPCIA was more stable during the measurement process and consumes lesser power.
20 citations
22 May 2021
TL;DR: A novel curvature compensation scheme is proposed and validated across PVT simulations and achieves 12 ppm/°C with a single point trim and eases the opamp’s requirements on offset and flicker noise significantly and doesn’t require sophisticated techniques, such as chopping.
Abstract: In this paper, a curvature-compensated bandgap reference circuit is presented which generates 0.538V from 0.85V supply voltage. The PTAT voltage generated in the bandgap core is added to the partial CTAT voltage to generate the sub-bandgap reference, reducing the CTAT current mirror mismatch. Furthermore, this architecture eases the opamp's requirements on offset and flicker noise significantly and doesn't require sophisticated techniques, such as chopping. A novel curvature compensation scheme is proposed and validated across PVT simulations and achieves 12 ppm/°C with a single point trim. The proposed bandgap consumes a power of 15 μW and occupies an area of 7315 μm2 in TSMC 28nm.
19 citations
10 Jun 2021
TL;DR: In this article, a self-bias opamp has been exploited to minimize the systematic offset in conventional BGR circuits, and a current mirror-assisted technique has been proposed to enable BGR operational at 0.82-1.05V supply without having any degradation in the performance while keeping the integrated noise of 15.2µV and accuracy of 23.4ppm/°C.
Abstract: Traditional BGR circuits require a 1.05V supply due to the V BE of the BJT. Deep submicron CMOS technologies are limiting the supply voltage to less than 940mV. Hence there is a strong motivation to design them at lower supply voltages. The supply voltage limitation in conventional BGR is described qualitatively in this paper. Further, a current mirror-assisted technique has been proposed to enable BGR operational at 0.82V supply. A prototype was developed in 65nm TSMC CMOS technology and post-layout simulation results were performed. A self-bias opamp has been exploited to minimize the systematic offset. Proposed BGR targeted at 450mV works from 0.82-1.05V supply without having any degradation in the performance while keeping the integrated noise of 15.2µV and accuracy of 23.4ppm/°C. Further, the circuit consumes 21µW of power and occupies 73*32µm2silicon area.
15 citations
TL;DR: In this paper, a method of realizing voltage-mode (VM) non-inverting high-pass filter (HPF), band-pass filters (BPF), low-pass filtering (LPF), and inverting low pass filter (ILPF) transfer functions structure with two grounded capacitors and four resistors through an analytical synthesis method is presented.
Abstract: In this paper, a method of realizing voltage-mode (VM) non-inverting high-pass filter (HPF), band-pass filter (BPF), low-pass filter (LPF), and inverting low-pass filter (ILPF) transfer functions structure with two grounded capacitors and four resistors through an analytical synthesis method is presented. The synthesis structure of the VM biquadratic filter consists of a voltage proportional block and two voltage lossless integrators based on the use of current feedback operational amplifiers (CFOAs). It is demonstrated that the derived biquadratic filter structure can simultaneously realize VM HPF, BPF and ILPF transfer functions or VM BPF and LPF transfer functions at a high-input impedance terminal. The VM biquadratic filter can independently adjust the resonance angular frequency and quality factor. By slightly modifying the proposed biquadratic filter, a VM quadrature sinusoidal oscillator can be achieved. The proposed biquadratic filter and quadrature oscillator have been simulated by OrCAD PSpice and appropriate hardware has been implemented with AD844-type CFOAs. In order to reduce power consumption, reduce chip area, reduce costs, and improve system integration, integrated VM CFOA-based biquadratic filter circuits and quadrature oscillator circuits are very important. The proposed filter and quadrature oscillator have been further fabricated in $0.18~\mu \text{m}$ 1P6M CMOS process technology. The entire chip area is 0.974 mm2, including a filter chip cell and an oscillator chip cell. Under the supply voltage of ±0.9 V, the total power dissipation of the filter chip cell is 5.4 mW, and the figure-of-merit (FOM) of filter chip cell is 66.7%. The measured value of the third-order intermodulation distortion of the filter chip cell is −55.29 dBc and the third-order intercept point is 19.9 dBm. The measured phase noise of CFOA-based filter chip cell at 1 kHz offset is less than −99.76 dBc/Hz.
14 citations
TL;DR: Five circuits of meminductor emulators have been proposed using two operational amplifiers, one memristor, three resistors and one capacitor, whereas the sixth circuit uses two operational Amplifiers, two memristors, one resistor and two capacitors.
Abstract: This paper presents six different meminductor emulator circuits based on operational amplifiers. Five circuits of meminductor emulators have been proposed using two operational amplifiers, one memr...
14 citations
01 Jan 2021
TL;DR: In this chapter, a converter designed to utilize input source to produce multiple output ratios is presented and the major contribution of the proposed circuit is to obtain maximum voltage conversion ratios with reduced number of switches and capacitors.
Abstract: DC-DC converter is to provide a predetermined and constant output voltage to a load from a poorly specified or fluctuating input voltage source. Switched-capacitor (SC) DC-DC power converters are a subset of DC-DC power converters which efficiently convert one voltage to another with the use of a network of switches and capacitors. Unlike traditional inductor-based DC-DC converters, switched capacitor converters do not depend on magnetic energy storage elements like inductors which increase the complexity of the circuit and also reduce the circuit efficiency. In this chapter, a converter designed to utilize input source to produce multiple output ratios is presented. The proposed converter circuit has a capability to reconfigure its gain using variable circuit structure by selectively activating converter switches by changing the pulses given to the switches which in turn produces both positive and negative voltage ratios. The same switches and capacitors are reused and connected in a predetermined pattern to generate the required output voltage optimizing the usage of the components. The proposed circuit uses four flying capacitors for charging and discharging the voltages, one output capacitor which is ten times of the flying capacitors value used for filtering any ripples in the output voltage, 13 active switches of MOSFETs used to achieve the required output with only one input voltage. It supports various voltage conversion ratios such as 5/1, 4/1, 3/1, 2/1, 1/2, 2/3, 1/5, 1/11, 1/21, 1/31, 1/41, 1/16, 3/43, 2/7, 3/13, 1/6. Out of these conversion ratios, four are of up modes which lift the voltage and 12 are of down ratios. Due to the continuous power supply reduction, positive output ratios of switched-capacitor circuits are widely used in electric vehicle for electronic devices such as audio controller, charging system and LED light and the negative output ratios to find applications in operational amplifiers. While SCs are only capable of a finite number of conversion ratios, SC converters can support a higher power density, smaller size compared with traditional converters for a given conversion ratio. Finally, through simple control methods, regulation over many magnitudes of output power is possible while maintaining high efficiency. The major contribution of the proposed circuit is to obtain maximum voltage conversion ratios with reduced number of switches and capacitors. The working principle, conversion ratios, modeling considerations in different conversion modes, the output waveform results for the voltage ratios and equivalent resistance of the proposed circuit are also explained.
14 citations
TL;DR: This brief investigates the output-feedback control problem with redundant channels, in which the output measurements may suffer from the Markov analog fading when transmitting through the independent primary channel and redundant channels.
Abstract: This brief investigates the output-feedback control problem with redundant channels, in which the output measurements may suffer from the Markov analog fading when transmitting through the independent primary channel and redundant channels. The actual channel mode obeys a two-state time-homogeneous Markov chain, and the expectation of fading amplitude in the good mode is much higher than the one in the bad mode. The mode detectors are employed to estimate the status of both the primary and redundant channels, by which the better measurement signals may be selected for the controller. Thus, a token-dependent output-feedback controller is constructed, and then, the stability condition is obtained via the actual mode-dependent Lyapunov function method. Finally, the proposed output-feedback control scheme is applied to an operational amplifier (OPA) circuit under the hidden Markov analog fading channels.
TL;DR: A bulk-driven low-impedance compensation technique is proposed for ultra-low supply voltage amplifiers by using the low resistance node of the current mirror of input, the efficiency of Miller compensation capacitor is greatly improved.
Abstract: A bulk-driven low-impedance compensation technique is proposed for ultra-low supply voltage amplifiers. By using the low resistance node of the current mirror of input, the efficiency of Miller compensation capacitor is greatly improved. By using this compensation method, a rail-to-rail input & output bulk-driven fully differential operational amplifier is also presented in the paper. The effectiveness of the circuit has been verified in a 65 nm CMOS process, the proposed three-stage amplifier has over 70.69 dB gain, 19.95 kHz gain-bandwidth product, and 69.7° phase margin while consuming only 8.72 nW power, and occupying die area of 0.00082 mm2 from a 0.3 V supply while driving a 100pF load.
TL;DR: In this article, a two-stage class A-AB operational amplifier (Op-Amp) is presented, where a boosted recycling folded cascode with more than four cascode transistors compared to the conventional structure is used in the first stage.
Abstract: A high-gain two-stage class A–AB operational amplifier (Op-Amp) is presented. A boosted recycling folded cascode with more than four cascode transistors compared to the conventional structure is used in the first stage of the proposed Op-Amp. The AB class output stage is constructed using a quasi-floating-gate MOSFET and a bootstrap capacitor. Indirect feedback compensation is utilized, leading to smaller compensation capacitors and, therefore, higher slew rate (SR) and bandwidth. The proposed circuit is simulated by using a 180-nm 1.8-V CMOS process standard technology. Simulation results with a 50-pF capacitance load show that DC gain, GBW, average SR, average 1% settling time, and phase margin (PM) are 121.6 dB, 45.3 MHz, 66.2 V/μS, 29.7 nS, and 65.6°, respectively. The PM and SR reduce to 65.6° and 51.9 V/μS, respectively, when driving a 100-pF capacitance load. The proposed Op-Amp consumes 1.59 mW @ 1.8 V, which makes it a high-current-efficiency two-stage amplifier.
TL;DR: In this article, a bio-medical amplifier with programmable gain and bandwidth is presented, which can accommodate different signals with a bandwidth ranging from 50 Hz up to 10 kHz to detect different bio-potential signals: EEG, ECG, EMG, PCG, and Aps.
Abstract: This work presents a bio-medical amplifier with programmable Gain and Bandwidth. The bandwidth of the proposed amplifier is controlled by tuning the unity-gain bandwidth (UGBW) of a rail-to-rail CMOS operational amplifier. The amplifier gain is controlled by changing the input capacitors keeping the bandwidth unchanged. The proposed bio-medical amplifier capable to accommodate different signals with a bandwidth ranging from 50 Hz up to 10 kHz to detect different bio-potential signals: EEG, ECG, EMG, PCG, and Aps, using fixed and small load capacitance. The proposed bio-medical amplifier consists of two stages each one designed with Tera ohm CMOS pseudo-resistors used in the amplifier feedback. The lower cutoff frequency of the bio-medical amplifier is tuned using two biasing currents in the CMOS pseudo-resistors, while two biasing voltages in the CMOS op-amps tune the higher cutoff frequency. The gain of the proposed bio-medical amplifier is ranging from 44.3 dB to 65.1 dB. High stability of the CMOS based op-amps (phase margin ≥60°) over the whole Gain and Bandwidth ranges is achieved. The overall power consumption of the bio-medical amplifier is less than 3.28 μW at the maximum gain settings of 65 dB and a maximum bandwidth of 10 k Hz. The total harmonic distortion of the proposed amplifier less than 1.21% for an input amplitude of 1 mVpk-pk over the entire bandwidth. The Input referred noise spectral density is 426 n V / Hz @1 kHz for the maximum bandwidth settings. The proposed bio-medical amplifier achieves an IIP3 value of 19.44 dBm for the amplifier gain of 54.9 dB. The simulation results show that the proposed bio-medical amplifier is robust against the PVT variations. LT-spice simulations using the standard 90 nm CMOS technology under 1 V supply voltage are performed to validate the theoretical results of the proposed amplifier.
TL;DR: A TCM based on multigradient neural network (MNN) using computational graph in the PyTorch framework is developed, which enables more precise circuit simulation for analog and RF circuits, and provides a rapid solution for early stage design technology cooptimization (DTCO).
Abstract: Transistor compact model (TCM) is the key bridge between process technology and circuit design. Typically, TCM is desired to capture the nonlinear device electronic characteristics and their high-order derivatives. However, for the novel devices in advanced and future technologies, establishing TCM based on analytical equations and extracting model parameters becomes tedious. The model fitting capability for device outputs’ high-order derivatives is also limited. These drawbacks hinder fast and accurate device to circuit evaluation cycles. We develop a TCM based on multigradient neural network (MNN) using computational graph in the PyTorch framework. This MNN model is able to simultaneously capture the transistor dc/ac characteristics, such as ${I}-{V}/{Q}-{V}$ , their derivatives ( ${G}-{V}/{C}-{V}$ ), and higher order derivatives accurately. Moreover, the model architecture can be widely adapted to various device types. Based on this model scheme, software is developed to enable the automated model generation for standard SPICE simulation. Finally, the model and software are validated for novel gate-all-around (GAA) Si cold source field-effect transistors (CSFET), and 19-stage ring oscillator and two-stage operational amplifier circuit simulations have also been demonstrated. This work reduces the cycle of novel device compact model creation and circuit benchmark simulation from months or weeks to hours. In addition, it enables more precise circuit simulation for analog and RF circuits, and it provides a rapid solution for early stage design technology cooptimization (DTCO).
TL;DR: This study aims to figure out the most widely used CP design topologies for embedded systems on the chip (SoC) by discussing the outline of appropriate schemes and recommendations to future researchers in selecting the most suitable CP design methods for low power applications.
Abstract: Applications such as non-volatile memories (NVM), radio frequency identification (RFID), high voltage generators, switched capacitor circuits, operational amplifiers, voltage regulators, and DC–DC converters employ charge pump (CP) circuits as they can generate a higher output voltage from the very low supply voltage. Besides, continuous power supply reduction, low implementation cost, and high efficiency can be managed using CP circuits in low-power applications in the complementary metal-oxide-semiconductor (CMOS) process. This study aims to figure out the most widely used CP design topologies for embedded systems on the chip (SoC). Design methods have evolved from diode-connected structures to dynamic clock voltage scaling charge pumps have been discussed in this research. Based on the different architecture, operating principles and optimization techniques with their advantages and disadvantages have compared with the final output. Researchers mainly focused on designing the charge pump topologies based on input/output voltage, pumping efficiency, power dissipation, charge transfer capability, design complexity, pumping capacitor, clock frequencies with a minimum load balance, etc. Finally, this review study summarizes with the discussion on the outline of appropriate schemes and recommendations to future researchers in selecting the most suitable CP design methods for low power applications.
TL;DR: This paper presents a quantum version of feedback amplification, where the general phase-preserving quantum amplifier and coherent feedback are employed to construct systems that produce several useful functionalities; quantum versions of differentiator, integrator, self-oscillator, and active filters.
Abstract: Feedback amplification is a key technique for synthesizing various functionalities, especially in electronic circuits involving op amps This paper presents a quantum version of this methodology, where the general phase-preserving quantum amplifier and coherent (ie, measurement-free) feedback are employed to construct various types of systems having useful functionalities: quantum versions of differentiator, integrator, self-oscillator, and active filters The class of active filters includes the Butterworth filter, which can be used to enhance the capacity of an optical quantum communication channel, and the nonreciprocal amplifier, which enables measurement of a superconducting qubits system as well as protection of it by separating input from output fields A particularly detailed investigation is performed on the active phase-canceling filter for realizing a broadband gravitational-wave detector; that is, the feedback-amplification method is used to construct an active filter that compensates the phase delay of the signal and eventually recovers the sensitivity in the high-frequency regime
TL;DR: In this article, four fully uncoupled quadrature sinusoidal oscillators, using two current differencing buffered amplifiers (CDBAs), four/five resistors and two capacitors have been presented.
Abstract: Four new circuits of fully uncoupled quadrature sinusoidal oscillators, using two current differencing buffered amplifiers (CDBAs), four/five resistors and two capacitors have been presented. In contrast to all previously published CDBA-based, fully decoupled, quadrature sinusoidal oscillators in which one of the input terminals is left unutilized, the presented circuits are realized by utilizing the intrinsic current differencing property of CDBAs, thus utilizing all the four terminals of the CDBA. All these quadrature oscillator (QO) circuits have an inherent feature of amplitude control of output voltages without using external control circuitry. Out of the four proposed QO circuits, two circuits have the additional feature of generating low-frequency oscillations, thus making them capable of generating wide range of frequency waveforms. The proposed oscillator circuits also possess additional functionalities not available in other CDBA-based quadrature sinusoidal oscillator circuits presented previously. The workability of the proposed circuits has been confirmed through experimental results where CDBAs are implemented using commercially available current feedback operational amplifiers (AD844).
03 Mar 2021
TL;DR: In this article, a driver amplifier suitable for fully differential low-frequency Successive approximation register analog to digital converter (SAR ADC) with 14-bit resolution is presented, where indirect feedback compensation is implemented for the compensation of a fully differential two-stage operational amplifier (op amp).
Abstract: This work presents a driver amplifier suitable for fully differential low-frequency Successive approximation register analog to digital converter (SAR ADC) with 14 bit resolution. The indirect feedback compensation technique is implemented for the compensation of a fully differential two-stage operational amplifier (op amp). The global common mode feedback (CMFB) circuit fix output common mode (CM). The PMOS input device reduces flicker noise at low frequency. The op amp design produces 73dB DC gain and 64 PM. The driver takes single-ended or fully differential input, consumes 430μW from 1.8V supply, has −93dB total harmonic distortion (THD) for 2V PP differential output.
24 May 2021
TL;DR: In this paper, the authors proposed digital potentiometer (DPOT) as a part of closed-loop self-calibration for Rogowski switch-current sensor (RSCS) on enhanced GD.
Abstract: In medium-voltage (MV) applications high-density, high-efficiency converters are necessity. Novel switching-cycle capacitor voltage control (SCCVC) for the modular multilevel converters (MMC) in combination with latest generation of SiC MOSFET devices will enable converters to meet those specifications. To enable SCCVC high-bandwidth Rogowski switch-current sensor (RSCS) is integrated on the gate driver (GD) to serve as peak-current-mode control sensor. Issues of RSCS OpAmp integrator non-idealities have to be resolved in order to achieve high accuracy. Due to often temperature swings and reduced lifetime, mechanical potentiometer is not preferred solution. As an alternative, this paper proposes digital potentiometer (DPOT) as a part of closed-loop self-calibration for RSCS on enhanced GD. Proposed method has high resolution of 98.6μV to eliminate input offset voltages, fast self-calibration finished in maximum 12.45ms, with maximum error of ±2.5A of RSCS current sensor. Experimental results at 6kV, 80A, 10kHz, switching as fast as 100V/ns show great accuracy of RSCS sensor, with minimum drifting.
13 Sep 2021
TL;DR: In this article, an internally compensated two-stage operational amplifier fabricated using unipolar a-IGZO TFT devices integrated on flexible polyimide substrate is introduced to realize high incremental impedance and serve as the stage load of the amplifier.
Abstract: This paper presents an internally compensated two stage operational amplifier fabricated using unipolar a-IGZO TFT devices integrated on flexible polyimide substrate. A new active load configuration is introduced to realize high incremental impedance and serve as the stage load of the amplifier. The opamp has been manufactured and measured to have 57 dB of open-loop DC-gain and a unity gain frequency of 311 kHz. Further, the internal compensation sets the dominant pole of the opamp achieving a phase margin of 75 degrees. A common mode feedback scheme has been implemented to bias the fully differential gain stages using an auxiliary two-stage OpAmp realized with a conventional diode-connected transistor stage load. This design, to our knowledge, surpasses the highest reported performance of (operational) amplifiers made in a-IGZO technology.
22 Mar 2021
TL;DR: In this article, a CMOS bio-medical amplifier based on a pseudo-resistor operating in the weak inversion region is presented, which is utilized as a feedback element in the first and second stage of the two-stages bio medical amplifiers in the portable bio-detection system.
Abstract: This work presents the design of a CMOS bio-medical amplifier using $\mathrm{T}\ \Omega$ pseudo-resistor based on MOS transistors operating in the weak inversion region. The pseudo-resistor is utilized as a feedback element in the first and second stage of the two-stages bio-medical amplifiers in the portable bio-detection system. Analytical analysis and simulations in LT-spice using 130 nm CMOS technology are performed to validate the realization of the extremely high resistance which can be reached to over tens of $\mathrm{T}\ \Omega$ . The simulation of the two-stages bio-medical amplifier based pseudo-resistor are carried out in LT-spice using ± 0.6 V supply. The LT-spice simulation results are confirming with both the results obtained by the MATLAB and the analytical analysis of the pseudo-resistor.
TL;DR: In this paper, a high-pass sigma-delta modulator (HPSDM) is proposed for ECG signal acquisition system using op-amp sharing and programmable feedforward coefficients.
Abstract: A high-pass sigma–delta modulator (HPSDM) is proposed for electrocardiography (ECG) signal acquisition system. The HPSDM is implemented using operational amplifier (op-amp) sharing and programmable feedforward coefficients. The op-amp sharing is adopted to reduce the quantity of amplifiers because they dominate the power consumption of the HPSDM. In addition, given that the magnitude of the ECG is dependent on different persons, programmable feedforward coefficients are utilized to extend the dynamic range of the HPSDM to fit the actual application. The proposed HPSDM is fabricated in a 0.18-μm standard CMOS process. Measurement results reveal that the proposed HPSDM has a signal-to-noise and distortion ratio (SNDR) of 54.5 dB and a power consumption of 2.25 μW under a 1.2 V supply voltage and achieves a figure of merit (FoM) of 12.96 pJ/conv. Moreover, the proposed HPSDM has an SNDR of 64.8 dB and a power consumption of 5.2 μW under a 1.8 V supply voltage and achieves a FoM of 9.15 pJ/conv due to the op-amp sharing technique. Under the 1.2 V and 1.8 V supply voltages, the dynamic range of the HPSDM is extended to approximately 12 dB due to the technique of programmable feedforward coefficients.
TL;DR: In this paper, a new circuit proposal for precision rectification, which is designed using current feedback operational amplifiers, is presented, and the new proposed circuit operation is clearly discussed.
Abstract: This article is devoted to a new circuit proposal for precision rectification, which is designed using current feedback operational amplifiers The new proposed circuit operation is clearly discuss
TL;DR: In this article, an electronic circuit with passive and active components associated with piezoelectric transducers QP10W was developed to produce a negative capacitance shunt circuit, implemented through Negative Impedance Converters (NIC) and using operational amplifiers.
Abstract: The need for control or suppression of vibrations in mechanical structures has arisen because of their damaging effects on people, civil structures and machine parts The present work aims to perform the vibration control of a portico type structure with two degrees of freedom, using piezoelectric transducers associated with negative capacitance shunt circuits with series electrical resistance For this purpose, an electronic circuit with passive and active components associated with piezoelectric transducers QP10W was developed to produce a negative capacitance shunt circuit, implemented through Negative Impedance Converters (NIC) and using operational amplifiers The response amplitudes of the system in the time domain and the frequency in free and forced vibration were analyzed in tests performed with and without shunt circuit operation in the system Considering free vibration, a reduction of 901 dB was obtained for the first natural frequency and of 695 dB for the second one For forced vibration, reductions of 15 dB were obtained for the first natural frequency and 219 dB for the second natural frequency, respectively The vibration reductions obtained with the proposed system demonstrate the efficiency of the system
22 Mar 2021
TL;DR: A cost-efficient HV amplifier suitable for driving capacitive loads such as dielectric elastomer (DE) loudspeakers within a typically used bandwidth for audio applications and the proposed topology’s suitability for driving DE loudspeakers and other possible use cases is presented.
Abstract: This paper presents a cost-efficient HV amplifier suitable for driving capacitive loads such as dielectric elastomer (DE) loudspeakers within a typically used bandwidth for audio applications. First, the unique challenges, especially considering voltage range, dynamics, and distortion posed on electronics driving DE loudspeakers, are examined. Subsequently, the suitability of different types of output stages for the intended purpose is discussed. The developed topology capable of driving capacitive loads at high voltages is then introduced. Its significant advantages are the small number of expensive high-voltage (HV) semiconductors, its high bandwidth and linearity at a low quiescent current. The authors analytically examine the amplifier’s operation and discuss the selection as well as the dimensioning of different key components. The driver stage contains a cascaded voltage-current-control loop realized with operational amplifiers, ensuring the power stage HV semiconductors’ appropriate driving. Tuning the control loop to the intended behavior is achieved with the method of pole placement. Thereby, the closed-loop control guarantees excellent command response from DC to 20 kHz and good disturbance suppression. Using a prototype with a maximum output voltage of 2500 V and a maximum output current of ±20 mA, the converter’s behavior is experimentally examined. Measurements focusing on frequency response, output power, and the total harmonic distortion show the topology’s excellent HV and audio characteristics. After presenting the prototype’s cost distribution, the authors finally discuss the proposed topology’s suitability for driving DE loudspeakers and other possible use cases.
TL;DR: In this article, a control circuit for the auxiliary buck/boost converter was designed and implemented to improve the load transient response of the buck converter, which shapes the auxiliary inductor current in the critical conduction mode through peak current mode control.
Abstract: A control circuit for the auxiliary buck/boost converter was designed and implemented to improve the load transient response of the buck converter. The circuit shapes the auxiliary inductor current in the critical conduction mode through peak current mode control. The soft-switching operation of the auxiliary switches minimizes the power loss and thus increases the efficiency of the auxiliary converter. Along with the design guidelines and estimated power loss to improve the performance of the proposed control technique, the implementation of the control circuit is explained in detail. Simple analog ICs such as operational amplifiers and comparators, and a couple of logic gates suffices the realization of the proposed control. A prototype buck converter whose input voltage, output voltage, and switching frequency were 15 V, 3.3 V, and 200 kHz, respectively were tested with the implemented control circuit to verify the performance of the proposed control technique.
14 Jun 2021
TL;DR: In this paper, an offset compensation method of the switching current sensor for the current control of the three-phase SiC inverter is proposed, which eliminates the op amp offset voltage and bias current effect on the sensor output.
Abstract: This paper proposes an offset compensation method of the switching current sensor for the current control of the three-phase SiC inverter. Switching current sensors with Rogowski coils, which have analog signal processing circuits implemented with the operational amplifier (op amp), are integrated into the four-layer PCB gate drive board; in the end, the phase currents are reconstructed with the op amp subtractor. To eliminate the op amp offset voltage and bias current effect on the sensor output, an offset compensation S/W algorithm is proposed. A three-phase SiC inverter prototype was built and tested with the three-phase load to verify the feasibility of the method.
TL;DR: The proposed 13-bit MC ADC, which uses a 4-bit single-slope (SS) quantizer as a sub-ADC, resolves the sampled input voltage, followed by the cyclic SS quantization operation that repeatedly produces and quantizes the residue voltage, thus achieving high conversion speed.
Abstract: This brief proposes a high-speed and power-efficient multi-bit cyclic analog-to-digital converter (MC ADC) for CMOS image sensor applications. The proposed 13-bit MC ADC, which uses a 4-bit single-slope (SS) quantizer as a sub-ADC, resolves the sampled input voltage, followed by the cyclic SS quantization operation that repeatedly produces and quantizes the residue voltage. It operates in only seven phases to resolve 13-bit, thus achieving high conversion speed. Moreover, the 4-bit SS quantizer employs a simple and power-efficient structure that includes only the analog circuits of an operational amplifier and a comparator. A test chip with the proposed MC ADC was fabricated using a 0.18- $\mu \text{m}$ standard CMOS process technology. The measurement results show that the proposed MC ADC achieves a differential nonlinearity of +0.5/−0.54 LSB and an integral nonlinearity of +1.7/−2.8 LSB. In addition, the maximum signal-to-noise- and-distortion ratio and the effective number of bits are measured to be 73.14 dB and 11.86-bit, respectively. The measured power consumption per channel is only 87 $\mu \text{W}$ at a sampling frequency of 781 kHz. Moreover, the figure of merit (FoM), which includes the power consumption per channel, row line time, and ADC resolution, is only 13.6 fJ/conversion, achieving the best FoM among the compared works. Therefore, the proposed MC ADC is suitable for CMOS image sensor applications requiring high conversion speed and low power consumption, such as digital single-lens reflex cameras and ultra-high-definition television broadcast cameras.