Showing papers on "Polysilicon depletion effect published in 1985"

Anomalous leakage current in LPCVD PolySilicon MOSFET's

Abstract: The anomalous leakage current I L in LPCVD polysilicon MOSFET's is attributed to field emission via grain-boundary traps in the (front) surface depletion region at the drain, and an analytic model that describes the strong dependences of I L on the gate and drain voltages is developed. The model predictions are consistent with measured current-voltage characteristics. Physical insight afforded by the model implies device design modifications to control and reduce I L , and indicates when the back-surface leakage component is significant.

Experimental study of the minority-carrier transport at the polysilicon—monosilicon interface

Abstract: This paper presents the results of an experimental study designed to explore both qualitatively and quantitatively the mechanism of the improved current gain in bipolar transistors with polysilicon emitter contacts. Polysilicon contacts were deposited and heat treated at different conditions. The electrical properties Were measured using p-n junction test structures that are much more sensitive to the contact properties than are bipolar transistors. A simple phenomenological model was used to correlate, the structural properties with electrical measurements. Possible transport mechanisms are examined and estimates are made about upper bounds on transport parameters in the principal regions of the devices. The main conclusion of this study is that the minority-carrier transport in the polycrystalline silicon is dominated by a highly disordered layer at the polysilicon-monosilicon interface characterized by very low minority-carrier mobility. The effective recombination velocity at the n+polysilicon-n+monosilicon interface was found to be a strong function of fabrication conditions. The results indicate that the recombination velocity can be much smaller than 104cm/s.

Controlled boron doping of silicon

Abstract: A technique for doping a silicon body (10) with boron. The surface to be doped is typically a trench sidewall, to be used as a storage capacitor or for isolation. By providing a silicon dioxide diffusion control layer, (20) and a polysilicon source layer (30) that incorporates the boron, well-controlled boron doping over a wide concentration range can be obtained. Control of the doping transfer can be obtained by the choice of ambients, either dry or steam. Furthermore, removal of the silicon dioxide and polysilicon layers following the doping process is facilitated due to the etch selectivity possible between SiO2 and Si. If desired, the layers may remain on the silicon body.

Heavily doped polysilicon-contact solar cells

Abstract: We report the first use of a (silicon)/(heavily doped polysilicon)/(metal) structure to replace the conventional high-low junction or back-surface-field (BSF) structure, of silicon solar cells. Compared with BSF and back-ohmic-contact (BOC) control slimples, the polysilicon-back solar cells, show improvements in red spectral response (RSR) and open-circuit voltage. Measurement reveals that a decrease in effective surface recombination velocity S is responsible for this improvement. Decreased S results for n-type (Si:As) polysilicon, consistent with past findings for bipolar transistors, and for p-type (Si:B) polysilicon, reported here for the first time. Though the present polysilicon-back solar cells are far from optimal, the results suggest a new class of designs for high efficiency silicon solar cells. Detailed technical reasons are advanced to support this view.

Characterization of thermally oxidized n + polycrystalline silicon

Abstract: The properties of thermally grown silicon dioxide films on n+polysilicon are studied using cross-sectional TEM, and electrical measurements to evaluate conduction, electron trapping, destructive breakdown and wearout mechanisms. All of the above electrical parameters are found to be degraded by any increase in the degree of surface roughness at the oxide-polysilicon interface. Our results suggest that a significant improvement in the insulating properties of the SiO 2 films can be achieved if the polysilicon is initially deposited in the amorphous phase at 560°C rather than the polycrystalline phase at 620°C. For example, for dry-oxidized diffusion-doped films, there is an increase in oxide breakdown field from 3.0 MV . cm-1to 6.2 MV . cm-1, and a reduction in leakage (Fowler-Nordheim) current of two orders of magnitude. Furthermore, it is shown that the long-term reliability of n+polysilicon/SiO 2 /n+polysilicon structures is directly related to the degree of interface texture; i.e., a smoother interface will result in a significant reduction in electrical wearout and an increase in time to failure.

A polysilicon emitter solar cell

Abstract: A new solar cell structure is reported in which the emitter consists of a thin layer of in situ phosphorus-doped polysilicon deposited by a low-pressure chemical vapor deposition (LPCVD) techniques. The highest process temperature required to fabricate this structure is only 627°C. Although the use of a polysilicon emitter results in some degradation in blue response, both theoretical and experimental results are presented indicating that photocurrent densities in excess of 30 mA.cm-2are attainable under AM1 illumination. The low back-injection current associated with the polysilicon emitter has allowed a very high open circuit voltage of 652 mV to be obtained at 28°C in a cell illuminated to give a short circuit current density of 30 mA.cm-2.

Dependence of the work-function difference between the polysilicon gate and silicon substrate on the doping level in polysilicon

Abstract: We correlate the work-function difference φ ps 0between the polysilicon gate and the silicon substrate in an MOS system with the doping level and carrier concentration in polysilicon. Polysilicon was doped by ion implantation with arsenic and phosphorus. The doping level was varied from 1019to 1020cm-3. Hall measurements were used to determine the carrier concentration in polysilicon at a given doping level. The Hall mobility and resistivity as a function of doping level were also obtained. The work function difference φ ps 0was determined by capacitance-voltage measurements on polysilicon-SiO 2 -Si capacitors with different oxide thicknesses. When plotted against the doping level, the work-function difference had a maximum at a dopant concentration of ≈ 5 × 1019cm-3, which corresponds to an electron concentration of 1.5 × 1019cm-3. At higher doping levels the value of φ ps 0decreases. The results can not be fully understood in terms of the Si band structure.

Correlation between the diffusive and electrical barrier properties of the interface in polysilicon contacted n + -p junctions

Abstract: The diffusion of As from polysilicon into boron-implanted single-crystal silicon through different interfaces obtained with different surface preparation techniques prior to polysilicon deposition is studied. The impurity profiles have been analyzed by SIMS and C-V measurements and ESCA has been used to determine the structural properties of the interface. Electrical measurements on diodes have been performed to study the diode characteristics and the electrical interface resistance. The diffusion through chemically grown oxide layers is found to be strongly retarded with respect to "oxygen-free" interfaces. A strong correlation appears to exist between the diffusive and electrical barrier properties of such interfaces. For increasing oxygen content at the interface, the minimum diffusion cycle required to obtain good diode ideality factors is higher as is the electrical interface resistance. We have observed an order of magnitude increase in the contact resistance for annealing temperatures between 800° and 900°C. One of the major conclusions is that the necessity to go to higher temperatures to decrease the series resistance of the polysilicon contacts in the case of chemically grown interface oxides is compromising their use in high-performance VLSI technologies.

Semiconductor integrated circuit vertical geometry impedance element

Abstract: A resistive load element comprises a Schottky barrier metal layer formed on the top surface of a doped p-type polycrystalline silicon (polysilicon) plug contacting a surface n+ zone located in a semiconductor body at a major horizontal surface thereof. The Schottky barrier metal layer is advantageously essentially a metal compound, such as titanium nitride, which does not react with the polysilicon and which forms a Schottky barrier contact with the polysilicon top surface of the plug. The polysilicon plug extends vertically down to the n+ zone through an aperture in an insulating layer that coats the major surface of the semiconductor body. The top surface of the Schottky barrier layer is coated with another metal layer, such as aluminum, for interconnection purposes. A pair of such elements can be integrated as loads, for example, in a static random access memory ("flip-flop") cell.

Process for making a lateral bipolar transistor in a standard CSAG process

Abstract: A method of forming a lateral bipolar transistor in a semiconductor substrate of a second conductivity type by an MOS or CMOS process which includes growing a thin insulating layer over the substrate and diffusing a tank region of a first type of conductivity into the semiconductor substrate of a polarity opposite to that of the second conductivity type. A strip of polysilicon is deposited around a region between the emitter area and collector area on a face of the substrate over said oxide. Next an emitter region having the form of a band enclosing an undiffused central region within the polysilicon strip and a collector region located outside of the strip are diffused into the tank. The polysilicon prevents diffusion of implanted impurity into the tank region over which is superimposed the polysilicon. An electrically conducting layer is formed over the emitter and a portion of the polysilicon. By using a strip of polysilicon to limit diffusion of the emitter and collector regions and by forming the emitter contact over both the emitter and polysilicon it is possible to achieve a smaller emitter geometry than is otherwise possible.

Use of selectively deposited tungsten for contact formation and shunting metallization

Abstract: A process for using selectively deposited tungsten in the making of ohmic contacts and contact/interconnect metallization patterns. In one form the process is employed to interconnect fully formed field effect devices using contacts through the dielectric layer. A thin layer of intrinsic polysilicon or amorphous silicon is conformally deposited, patterned and covered by selectively deposited tungsten, An anneal operation then forms self-aligned contacts or shunts, between the tungsten layer and the source/drain type diffusions exposed during the contact cut, by updiffusion through the thin intrinsic silicon, or by conversion of the thin intrinsic silicon to tungsten. Alternatively, contacts and shunts can be formed using polysilicon layers without regard to impurity type by making contact cuts through the dielectric to expose substrate regions, patterning a deposited polysilicon layer to cover only parts of such exposed regions, forming the field effect device source/drain regions, and then selectively depositing tungsten on all exposed surfaces of silicon. The tungsten thereby bridges the polysilicon layer to the adjacent, exposed substrate region and shunts all surface adjacent p-n junctions, including the polysilicon-to-substrate contact junction.

Self-aligned transistors with polysilicon emitters for bipolar VLSI

Abstract: A new bipolar process technology for fabricating self-aligned transistors with polysilicon contacted emitters is described. The extrinsic base regions of the transistor are self-aligned to the emitter contact by exploiting the effects of concentration-dependent oxidation to selectively oxidize the polysilicon. The shallow emitter is fabricated with a thin oxide layer at the polysilicon-silicon interface, thereby enhancing the emitter efficiency and thus the current gain of the device. It is demonstrated that this gain enhancement can be traded for a considerable increase in active base doping, with a resulting decrease in base resistance and potential improvement in switching performance. Under certain circumstances, non-ideal electrical characteristics can be obtained from the self-aligned transistor which are caused by lateral spread of the extrinsic base region beneath the sidewall oxide of the polysilicon emitter contact. This leads to the formation of p+-n+junction at the periphery of the emitter and hence to tunneling of carriers across this region. It is shown that the same tunneling mechanism also limits the extent to which the active base doping can be increased. In order to avoid the formation of the peripheral p+-n+junction, a polysilicon base contact is employed which allows a self-aligned extrinsic base region to be fabricated with negligible lateral movement.

Characteristics and Three-Dimensional Integration of MOSFET's in Small-Grain LPCVD Polycrystalline Silicon

Abstract: Building on nearly two decades of reported results for MOSFET's fabricated in small-grain polycrystalline silicon, a design methodology is developed that yields devices which have low threshold voltage, high drive current, low leakage current, tight parameteric control, and reduced topology, while requiring no nonstandard materials, processes, and tools. Design criteria and device performance are discussed, grain boundary characterization techniques are described, technological issues pertinent to VLSI implementation are investigated, and long-term device reliability is studied. The potential applications of the polysilicon MOSFET's in high-density dRAM and sRAM are explored. The successful implementation of an experimental stacked CMOS 64K static RAM proves the utility of these devices for three-dimensional integration in a VLSI environment.

High-gain bipolar transistors with polysilicon tunnel junction emitter contacts

Abstract: Experimental measurements of the dc gain as a function of temperature and of emitter-base and collector-base current-voltage characteristics for bipolar transistors with polysilicon contacts to the emitter are reported, dc gains as high as 2000 have been measured in devices for which a thin insulating layer was encouraged to grow between the monocrystalline silicon emitter and the polycrystalline silicon contact layer. This gain is 20 times larger than that for devices in which the insulating film growth was inhibited. It is suggested that, for these particular devices, the polysilicon layer contributes to a contact which is very similar to that of a metal-insulator-semiconductor tunnel junction contact. A model based on this hypothesis is developed and shown to give a good fit to all the experimental data.

An interlayer contact for use in a static ram cell

Abstract: A CMOS static RAM (10), which has P channel transistors (12, 14) formed in a second polysilicon layer (39, 40), N channel transistors (11, 13, 15, 16) formed in the substrate (48), and gates of both the N channel (11, 13, 15, 16) and P channel transistors (12, 14) formed in a first polysilicon layer (29, 30, 31, 32), requires that ohmic contact be made between semiconductor material of different conductivity type. The first polysilicon layer (29, 30, 31, 32) is N-type, and the second polysilicon layer (39, 40) is P-type. Ohmic contact therebetween is achieved by providing a silicide layer (35, 36) which is between these two layers and in physical contact with both. Ohmic contact between N-type regions (32) in the substrate (48) and the second polysilicon layer (39, 40) is similarly achieved by sandwiching silicide (34, 37) therebetween.

Method for fabricating stacked CMOS transistors with a self-aligned silicide process

Abstract: A method for siliciding interconnects on a vertically integrated device utilizing stacked CMOS technology includes a step for blocking off the p-channel devices. This blocking step is utilized to block the p-channel device in a stacked CMOS pair prior to forming titanium di-silicide on the exposed polysilicon interconnects. A mask is formed on the top polysilicon layer that forms the p-channel device and then patterned to remove the mask and the top polysilicon layer to expose the underlying polysilicon layers. A sidewall oxide is then formed to completely seal the p-channel devices and then the exposed silicon and polysilicon surfaces subjected to a self-aligned silicide process.

Low noise polycrystalline semiconductor resistors by hydrogen passivation

Abstract: Low noise polycrystalline silicon resistors are fabricated in the following sequence: (1) deposit an appropriate thickness of polysilicon (e.g. 400 nm) on top of an oxidized wafer (2) resistor doping by ion implantation (e.g. phosphorous) (3) heavy doping of the end-contact regions of the polysilicon resistor by high-dose ion implantation (4) patterning the polysilicon resistor (5) oxidation/annealing the polysilicon resistor (6) open contacts to the polysilicon resistor (7) aluminum metallization to form ohmic contacts (8) a long (e.g. 3 hours) low temperature (e.g. at 375°) pure hydrogen annealing to passivate the interface states in the polysilicon resistor. Polyresistors processed this way have a noise figure that is about a factor of three lower than samples processed otherwise. The low temperature post metallization annealing in pure hydrogen passivates the interfaces of polyresistors, reducing the l/f noise normally generated therein.

A true polysilicon emitter transistor

Abstract: A polysilicon emitter transistor has been fabricated in which the metallurgical base/emitter junction coincides with the interface between polycrystalline and monocrystalline material. The emitter region was formed by deposition of heavily phosphorus-doped polysilicon in an LPCVD reactor at 627°C, a temperature low enough to prevent diffusion of phosphorus into the substrate. Emitter Gummel numbers of over 1014scm-4have been obtained with this structure, allowing common emitter current gains in excess of 10000 to be reached for base implant doses of 1012cm-2.

Process for fabricating polysilicon resistor in polycide line

Abstract: In making a polysilicon resistor in a polycide line, a thick oxide is established selectively to shield lightly doped polysilicon first from heavy doping and then from the silicide. Before adding silicide, a selected region of polysilicon broader than and including the site of the poly resistor is exposed, lightly doped, and then oxidized to establish a thick oxide, while other areas are protected by nitride. Then the nitride and any thin oxide on top of the polysilicon outside the broad area are removed, and the exposed polysilicon is heavily doped for low resistivity. The thick oxide shields the underlying lightly doped polysilicon from the heavy doping. Silicide is then added. Definition of the polysilicon resistor follows preferably using a two step process. When the silicide is etched, the thick oxide on top of the broad polysilicon area acts as an etch stop. Then the thick oxide and polysilicon resistor are etched.

Modeling of accumulation-mode MOSFET's in PolySilicon thin films

Abstract: An analytic model of p-channel polysilicon MOSFET operating in accumulation mode is presented. The measured device transfer characteristics, for passivated and unpassivated films, are quantitatively explained in terms of leakage, subthreshold, and drive regimes of operation. The observed current swing of 104is shown to result primarily from the gate-voltage-induced mobility enhancement. This enhancement, a unique feature of polysilicon, is quantified via electrostatic shielding and barrier-potential-dependent mobility. The model describes transconductance, drain admittance, and ON/OFF ratio as a function of grain size, trap density and level, film thickness, and doping concentration.

Vertical bipolar transistors in laser-recrystallized polysilicon

Abstract: Vertical bipolar n-p-n transistors with a base width of 0.2 µm have been fabricated in laser-recrystallized polysilicon films on thermally oxidized silicon substrates. With proper hydrogen annealing steps, common-emitter current gains on the order of 100 were possible. Recombination in the base-emitter space-charge region was found to be the dominant source of base current.

Impact of processing parameters on base current in polysilicon contacted bipolar transistors

Abstract: A number of models have been presented to explain the lower base current in bipolar transistors with polysilicon emitter contacts: the effects of oxides (native and chemically grown) at the polysilicon-silicon interface; dopant segregation at this interface; and minority carder transport in the polysilicon. To differentiate between these models and to determine the process sensitivity of polysilicon contacted BJT's, a series of controlled experiments correlating physical structures with electrical characteristics have been performed. We find that for anneals at low temperatures and times (e.g., 900°C/1hr) the unintentional native oxide at the polysilicon-silicon interface dominates the electrical characteristics, resulting in extremely low base currents. For higher temperature anneals or doping levels above 2×1020/cm3, the native oxide layer breaks up and epitaxial regrowth of the polysilicon layer occurs. This reduces the blocking action of the interface and allows more carriers to enter the polysilicon, increasing the base current by as much as a factor of four.

Self-Aligned Transistors with Polysilicon Emitters for Bipolar VLSI

Abstract: A new bipolar process technology for fabricating self-aligned transistors with polysilicon contacted emitters is described. The extrinsic base regions of the transistor are self-aligned to the emitter contact by exploiting the effects of concentration-dependent oxidation to selectively oxidize the polysilicon. The shallow emitter is fabricated with a thin oxide layer at the polysilicon-silicon interface, thereby enhancing the emitter efficiency and thus the current gain of the device. It is demonstrated that this gain enhancement can be traded for a considerable increase in active base doping, with a resulting decrease in base resistance and potential improvement in switching performance. Under certain circumstances, non-ideal electrical characteristics can be obtained from the self-aligned transistor which are caused by lateral spread of the extrinsic base region beneath the sidewall oxide of the polysilicon emitter contact. Tlris leads to the formation of p/sup +/ -n/sup +/ junction at the periphery of the emitter and hence to tunneling of carriers across this region. It is shown that the same tunneling mechanism also limits the extent to which the active base doping can be increased. In order to avoid the formation of the peripheral p/sup +/-n/sup +/ junction, a polysilicon base contact is employed which allows a self-aligned extrinsic base region to be fabricated with negligible lateral movement.

Silicide‐Silicon Interface Degradation during Titanium Silicide/Polysilicon Oxidation

Abstract: The authors have investigated the silicide-silicon interface during the oxidation of titanium silicide on polysilicon. They find that during oxidation the polysilicon layer under the silicide is consumed inhomogeneously and that at the same time the titanium silicide moves into the polysilicon layer. Oxidations were carried out both in wet an dry O/sub 2/ with similar results. This nonuniform consumption of the polysilicon layer appears to be related to the condition of the silicide-silicon interface prior to the oxidation step. This effect can result in the reduction of the dielectric breakdown strength of underlying gate oxide in titanium silicide/polysilicon/oxide/Si structures.

Low Leakage Current Polysilicon Oxide Grown by Two-Step Oxidation

Abstract: The decrease in polysilicon oxide leakage current was experimentally investigated in the range of the oxide thickness from 14nm to 60nm. As a result, it was concluded that the suppression of the oxidation rate at an early stage of the oxidation reduced the conductance of the polysilicon oxide.

Manufacture of MOSFET with metal silicide contact

Abstract: Polysilicon elements of integrated circuits, for example gates (24) or interconnects, are provided with metallic silicide layers (26) in order to take advantage of the lower resistivity thereof. The polysilicon elements are defined on an oxide layer (23) disposed on a silicon substrate (20) before polysilicon metallization. After polysilicon metallization the metal and polysilicon are caused to interdiffuse to form silicide layers (26) covering the polysilicon elements (24).

Activation of polysilicon connections by selective CW laser annealing

Abstract: A new self-aligned procedure has been developed to connect polysilicon links on chip by using a CW argon laser. A silicon nitride mask serves as a diffusion barrier over part of the link during doping of the polysilicon, and later as an antireflection coating to couple the maximum amount of light into the undoped region during laser scanning. The laser melts this region only and dopant atoms rapidly diffuse in from the neighboring parts of the link. For the optimum mask length, 100 percent of the links were open circuits ( >15 MΩ) before irradiation, while the sheet resistivity was reduced to 12 Ω after processing.

Dual level polysilicon single transistor-capacitor memory array

Abstract: A self-aligned one transistor-capacitor memory cell is provided which uses an n-channel MOS transistor having separate drain and source regions with a first level polysilicon conductor coupled to the top plate of the capacitor and separate second level polysilicon conductors coupled to the gate and drain of the transistor. A reduction in a dimension of the memory cell is acheived compared to a similar memory cell which uses only one level of conductors.

Controlling the titanium silicide penetration into the polysilicon during oxidation of TiSi 2 /polysilicon structures

Abstract: It was found that during the oxidation of a titanium silicide/polysilicon structure, there is non-uniform consumption of the underlying polysilicon resulting in spiking of the silicide into the polysilicon layer. To eliminate this problem a layer of 400-600 A of a-Si was deposited in situ just prior to the deposition of the silicide, on top of the n+polysilicon layer. This structure did not show any spiking for a 60-min oxidation at 950°C in dry O 2 .