Showing papers on "Polysilicon depletion effect published in 1986"

Physics, technology, and modeling of polysilicon emitter contacts for VLSI bipolar transistors

Abstract: The physics of minority-carrier injection into polysilicon-contacted emitters has been studied through a series of experiments correlating the base current of the transistor to the structure of the polysilicon/single-crystal silicon interface. Most of the relevant material and processing parameters have been examined. In addition, a novel approach has been taken in the modeling of transport in these emitters to quantify the minority-carrier blocking properties of the polysilicon contacts. Experimental results show that extremely low values of base current can be obtained for devices etched in HF prior to the polysilicon deposition, i.e., devices with only a remnant "native" oxide layer at the polysilicon/single-crystal silicon interface. For these devices, the base current is mainly determined by the recombination and blocking of minority carriers at the polysilicon/monosilicon interface. A number of competing mechanisms exist in several domains of doping, temperature, and time which influence the properties of this interface. One of these mechanisms is the blocking of minority carriers by the native oxide layer itself. The uniformity and, consequently, the blocking characteristics of this layer were found to be strongly affected by the polysilicon doping level and thermal treatment.

Fabrication of double diffused metal oxide semiconductor transistor

Abstract: In the fabrication process of a DMOS transistor, a window is formed between polysilicon gate regions. Nitrogen is then implanted in the window. A self-aligning oxide is deposited to cover the exposed side walls of the polysilicon gate regions. P-type impurities are implanted at the exposed surface of the window between the side walls. Using silicon nitride masking, an oxide plug is then grown in the window. N-type impurities are implanted in the window region to form a junction adjacent to the polysilicon gate regions. Metal contacts and a passivation layer are subsequently deposited by masking, and contact windows are formed to complete the transistor structure.

Method for making electrically programmable memory device by doping the floating gate by implant

Abstract: In the present invention, asperity in the floating gate of an EPROM or EEPROM device is reduced. An improved process for fabricating ultrahigh coupling interpoly isolation dielectrics comprising a structure of oxide-nitride-oxide is disclosed. The first oxide is grown on undoped LPCVD polycrystalline silicon (polysilicon) to reduce the grain boundary-oxidation enhancement effect at the interface of floating gate polysilicon and interpoly oxide. This results in much higher breakdown capability of interpoly dielectrics. As a consequence, the shrinkage of the interpoly electrical thickness to an extent far beyond current limitation becomes possible. Implanted dopants through interpoly oxide into the floating gate polysilicon also eliminate the oxidation enhanced diffusion from conventional POCl 3 doped polysilicon into tunnel oxide. The phosphorus induced trap in the tunnel oxide region are reduced. The EEPROM threshold window can remain open beyond 10 6 cycles.

Method of making a memory device with polysilicon electrodes

Abstract: A semiconductor memory device is provided with a memory region including SAMOS type memory transistors and a non-memory or peripheral region including MOS transistors which are interconnected to form logic circuits such as decoders for controlling the operation of each of said memory transistors. Each of the transistors includes a pair of first and second doped polysilicon layers and an interlayer insulating film provided as sandwiched between the pair of first and second doped polysilicon layers. In the memory region, the first and second doped polysilicon layers define floating and control gate electrodes, respectively; whereas, in the non-memory region, the first and second doped polysilicon layers are electrically interconnected by a through-the-layer electrode formed through the interlayer insulating film.

Integrated circuit device and process with tin capacitors

Abstract: A new integrated circuit structure, wherein a TiN thin film layer 129 and another patterned thin film layer 124 preferably comprising polysilicon are separated (in some locations) by a thin dielectric 132 to define capacitors. At various other locations, the TiN layers 129 also makes contact to the polysilicon layer 124 (which will be silicide-clad at these locations), makes contact to n+ substrate regions 134 and p+ substrate regions 136, and also to provide a contact pad for a third patterned thin film conductor layer which overlies the other two. One important class of embodiments provides a floating-memory cell. wherein the floating gate 120 is made of polysilicon, but the control gate 142 consists predominantly of titanium nitride. A novel process for forming the titanium nitride control gate 142 and simultaneously forming titanium nitride local interconnect lines 149 is also disclosed.

Plugged poly silicon resistor load for static random access memory cells

Abstract: An improved process for fabricating a static RAM cell having a polysilicon load resistance is provided. Following formation of source, gate and drain regions, a planarized dielectric structure is formed over the junction regions, and via openings which expose portions of the source and drain regions are created. The via openings are filled with polysilicon interconnects, appropriately doped for low resistance contacts. Where the contact includes a resistor load, the polysilicon is not doped. Thus, the prior art approach of providing doped and undoped regions along the same polysilicon interconnect is not employed. Rather, the doped and undoped regions are physically separated. Consequently, the minimum length of the poly load is limited only by the ability to form via openings of small dimensions.

High-speed polysilicon emitter—base bipolar transistor

Abstract: High-speed polysilicon emitter and base electrode Si n-p-n bipolar devices were fabricated showing performances of 55-ps ECL gate delay (FI = FO = 1) and cutoff frequency of 15.6 GHz (at V CE = 3 V, LV CEO = 6.8 V). These devices were built on an oxide-isolated substrate produced by planarizing oxide which is deposited after device Si island etching. The final emitter width is 0.5 µm, and a 1.3-µm-thick arsenic-doped LPCVD epitaxial layer of 0.25 Ω.cm is utilized. Emitter-base (E-B) junctions formed by direct implantations of arsenic and boron ions into a substrate were compared with junctions induced by diffusing dopants from implanted polysilicon. In the case of diffused junctions, an emitter junction depth of less than 500 A along with a 1000-A base width can be obtained.

Method for making static random-access memory device

Abstract: A method of making a static random-access memory device or SRAM including a memory cell having a high-resistance load element. The load element is formed from a polysilicon film, and an impurity is introduced into at least a part of the polysilicon film for the purpose of increasing the threshold voltage of a parasitic MISFET formed using the load element as its channel region. Alternatively, the deposition of the polysilicon film is carried out at a relatively high temperature, thereby preventing any increase in the current flowing through the load element, and thus reducing the power dissipation in the SRAM.

A MOS Transistor with self-aligned polysilicon source—drain

Abstract: A new MOS transistor with self-aligned polysilicon source-drain (SAPSD) is demonstrated. Using a thin implant-doped polysilicon layer above the active channel region, a shallow source-drain junction with negligible leakage is realized. A novel lightly doped-drain (LDD) structure is also incorporated by diffusing dopants from the n+ polysilicon source-drain layer into the silicon substrate, forming the n- region. During the gate oxidation, a sidewall spacer is simultaneously formed by the oxidation of polysilicon source-drain sidewalls. The transistor layout area is saved by bringing the source-drain contacts onto the field oxide region. Experimental results of the new structure are presented.

A high-speed bipolar LSI process using self-aligned double diffusion polysilicon technology

Abstract: A Self-aligned Double Diffusion Polysilicon technology (SDD), assisted by the method of fabricating self-aligned polysilicon base electrodes, has been investigated for the application to high-speed bipolar LSIs and VLSIs. Very shallow emitter-base junctions -- 50nm-deep emitter and 100nm-wide base -- have been realized. A combination of SDD with the self-aligned polysilicon base method enabled to establish a process of fabricating 0.4µm-wide emitters for NPN transistors. The process also realized the active regions of transistors free from damages and the steady reproducibitily of emitter-base double diffusion as well. Cut-off frequency of the transistor was 14GHz under the conditions of 600µA collector current and 3V collector-emitter voltage. Minimum propagation delay time of 72ps was measured by the 51-stage LCML ring-oscillator.

Majority and minority carrier transport in polysilicon emitter contacts

Abstract: The minority hole transport in polysilicon emitter contacts has been studied with a novel pnp test transistor. Segregated arsenic at the polysilicon/silicon interface is mostly responsible for the base current reduction in polysilicon-contacted npn transistors. This improvement comes at a price of a higher emitter resistance. This resistance was measured with a Kelvin resistor structure and the base current/ emitter resistance trade-off is quantified.

In-situ epitaxial silicon—oxide-doped polysilicon structures for MOS field-effect transistors

Abstract: Limited reaction processing (LRP) has been used to achieve the in-situ growth of epitaxial silicon-oxide-doped polysilicon layers. The in-situ growth of these multiple layers was combined with the selective epitaxial growth technique to create structures for MOSFET fabrication. The results of n- and p-channel transistor fabrication utilizing these structures are presented.

A comprehensive analytic model of accumulation-mode MOSFET's in PolySilicon thin films

Abstract: A comprehensive analytic description of the polysilicon (poly-Si) MOSFET, operating in the accumulation mode is presented. The model is not a single crystalline analog. Rather, the formulation is based upon structural and electronic properties inherent in poly-Si thin films. The model is capable of quantitatively explaining the bulk of reported device characteristics, specifically the temperature coefficient of current (TCC). Drive and leakage current as a function of doping level are also quantitatively discussed. In addition, transconductance, drain admittance, and ON/OFF current ratio are described extensively at room temperature and above and are compared with experimental data. The role of grain boundary hydrogenation in effecting the device performance is quantified. Finally, a few pertinent design guidelines are presented.

Hot-Electron Trapping and Generic Reliability of p + Polysilicon/SiO2/Si Structures for Fine-Line CMOS Technology

Abstract: The generic reliability of p+ polysilicon/SiO2/Si structure has been investigated using avalanche injection method on MOS capacitors. Hot-electron trapping in p+ polysilicon/SiO2/Si capacitors with 250A and 500A thick oxides was compared with n+ polysilicon/SiO2/Si capacitors. For the identical injection conditions, p+ polysilicon gate capacitors show larger threshold voltage shifts compared to n+ polysilicon gate capacitors with the same thickness. These threshold voltage shifts were significantly reduced after the standard low temperature H2 anneal. A correlation of hot-electron trapping before and after the hydrogen anneal indicates that boron atoms themselves do not act as electron traps in SiO2, but the presence of boron in SiO2 enhances the water-related electron traps. A model is proposed and supported by Infrared measurements on TEOS and BTEOS films.

Radiation-hardened n-channel MOSFET achieved by a combination of polysilicon sidewall and SIMOX technology

Abstract: A radiation-hardened n-channel MOSFET has been developed by a combination of a polysilicon sidewall and SIMOX technology. The MOSFET is laterally isolated by multilayers of sidewall SiO2, sidewall polysilicon and field SiO2, It is vertically isolated by multilayers of highly oxygen-doped polysilicon and buried oxide. By using this isolation structure and a thin gate oxide, an increase in leakage currents and a threshold voltage shift were suppressed to less than 1.5 orders of magnitude and 0.08 V, respectively, after 106 rad(Si) irradiation.

Semiconductor device with a high breakdown voltage

Abstract: There is disclosed a power transistor comprising a semiconductor substrate having a PN junction exposed on a major surface of the semiconductor substrate, and a semiinsulative polysilicon film formed on the major surface, the polysilicon film covering the PN junction, the polysilicon film containing at least one of carbon, oxygen, and nitrogen, and the polysilicon film having a thickness of about 3000 Å.

In situ arsenic-doped polysilicon for VLSI applications

Abstract: A novel process for the growth of in situ arsenic-doped polysilicon has been developed in a conventional low-pressure CVD reactor. The deposition parameters and the film properties have been investigated. The films have been applied to advanced bipolar transistors as emitter contact and arsenic diffusion source, and to CMOS DRAM's as capacitor contact and trench fill material. Thickness and resistivity uniformity, doping profiles within the poly and out-diffused into the single crystal and conformality of the films deposited in deep trenches are shown.

Fabrication of High Voltage Polysilicon TFT's on an Insulator

Abstract: Using thin film transistors in active‐matrixed addressed large area displays has recently become important in display development. Specifically, a PLZT ceramic dot‐matrix display requires high voltage TFT pixel switching. To meet the need, a process has been developed utilizing polysilicon and temperatures less than 850°C, which yields MOSFET's capable of operating at voltages in excess of 50V with high ratios. High mobilities are obtained by fabricating n‐channel, accumulation‐mode devices in silicon deposited in the amorphous state and later annealed to the final polycrystalline condition.

Polysilicon conductive layers integrated circuits

Abstract: Low resistivity doped polysilicon conductive layers are formed on an integrated circuit by low temperature recrystallisation of doped amorphous silicon followed by transient pulse annealing to a peak temperature of 1000 to 1 100 DEG C to activate the dopant. The pulse annealing effects a reduction in the resistivity compared with previous methods.

Process for forming contacts and interconnects for integrated circuits

Abstract: In a process for forming ohmic contacts and interconnects for an integrated circuit structure such as a CMOS device structure, a thin layer of intrinsic polycrystalline or amorphous silicon (22) is formed over the structure and patterned to leave portions of the polysilicon layer (22) at contact and interconnect locations. The structure is then heated in an inert atmosphere to updiffuse dopant from doped substrate regions into regions (24A, 25A) of the polysilicon in contact with the substrate surface. A layer of tungsten (26, 27) is selectively deposited on the polysilicon by a CVD process. The tungsten (26, 27) acts to shunt p-n junctions in the polysilicon and any undoped polysilicon. In a second embodiment a tungsten layer (42, 43, 44) is provided to bridge a polysilicon layer (32) to a substrate region (38) and to shunt surface-adjacent p-n junctions (37, 39).

Self-aligned polysilicon base contact structure

Abstract: An integrated bipolar transistor having a self-aligned polysilicon base contact is formed by depositing a first doped polysilicon layer and a silicon nitride passivating layer on the surface of a semiconductor substrate having an isolated collector region therein. An opening is formed in the first polysilicon and silicon nitride layers over the collector to expose the surface of the semiconductor substrate. The base region is formed through the opening and a conformal silicon nitride coating is then deposited on the wall of the opening and over the surface of the semiconductor substrate within the opening. A second polysilicon layer is formed on the silicon nitride passivating layer. The second polysilicon layer is reactive ion etched, leaving a polysilicon sidewall on the wall of the opening while removing the rest of the second polysilicon layer. The polysilicon sidewall is then oxidized, and an emitter is formed through the opening. The bipolar transistors of the present invention have high density, high speed and improved device to device uniformity because thinning or shorting of the passivating layer on the polysilicon layer is prevented.

Method for fabricating a bipolar semiconductor device by undercutting and local oxidation

Abstract: A method for fabricating bipolar transistors comprises a step of forming a multi-layered film consisting of a polysilicon film (600), a silicon nitride film (202) and a silicon oxide film (104) on an emitter region (7) and on an external base region (54, 56), a step of causing the silicon oxide film (104) to recede inwardly from the polysilicon film (600) and silicon nitride (202) film, a step of patterning the polysilicon film (600) by using the inwardly receded oxide film (104) as a mask while defining the external base region (54, 56), a step of forming an emitter region (7) and an active base region (6) by using the patterned polysilicon as an impurity diffusion source while self-alignedly forming an external base region (54, 56), and a step of self-alignedly forming an insulation film (107, 203) for electrical isolation between base and emitter electrode interconnections (9) on the side wall of the polysilicon film (603) by means of anisotropic etching.

Hydrogenation for PolySilicon MOSFET's by ion shower doping technique

Abstract: Hydrogenation using the ion shower doping technique has been proposed as a means of improving the ON/OFF ratio of both p-channel and n-channel polysilicon MOSFET's constructed with LPCVD polysilicon films. Hydrogen ions accelerated at a voltage as low as 0.5-2.0 kV have been doped on heated MOSFET's in the presence of an interdielectric layer and AI electrode. Our ion shower doping of 30 min at 470°C with a subsequent anneal of 30 min has improved drive and leakage current by two orders of magnitude and by one order of magnitude, respectively, on both p- and n-channel MOSFET's.

Method of eliminating titanium silicide penetration into polysilicon during the oxidation of a polycide structure.

Abstract: A novel method is described for use in IC technology for reducing the resistance of polysilicon interconnect lines. This is accomplished by placing a refractory metal silicide on the polysilicon interconnect material. In the preferred embodiment of this method, a layer of silicon is interposed between the polysilicon interconnect material and and a titanium silicide to eliminate penetration of the refractory metal silicide into the underlying polysilicon layer during the oxidation process of said structure both in dry and wet oxygen environments.

Fabricating semiconductor device with polysilicon protection layer during processing

Abstract: A method for making a semiconductor device having transistors comprising the active regions which are protected by polysilicon layer during the whole process from damages due to the other processing, that is dry etching, etc. and a minimized base region so as to provide a high operating speed and a minimium size thereof as well as lowest power consumption features.

Implanted-Silicided polysilicon gates for VLSI transistors

Abstract: Polysilicon MOS capacitors, silicided with titanium-silicide, and implanted with BF 2 or arsenic, were investigated to determine if low doping concentrations can be used to predictably set flat-band voltages. Experimental results show the flat-band voltages, for both arsenic- and BF 2 -implanted polysilicon, to be approximately equal to highly doped polysilicon and without any appreciable dependency on dose levels.

A device comprising a pair of CMOS FETs and a method of making it.

Abstract: All the gates and source/drain contacts in a CMOS device (1) are formed from polysilicon or polycide. Using two levels of polysilicon or polycide, the first level is used to simultaneously form the gate (10) of one (2) of the CMOS transistors and buried contacts (30, 31) to the source/drain regions (13, 14) of the other (3) CMOS transistor. The second level of polysilicon or polycide is then used to simultaneously form the gate (15) of the other (3) CMOS transistor and the buried contacts (28, 29) to the source/drain regions (8,9) of the first mentioned CMOS transistor. Because all the gates and contacts are polysilicon or polycide, it is possible to make interconnections between the gate on one of the devices and the source or drain of the other of the devices and between the gate on the other of the devices and the source/drain on said one of the devices simply by patterning the polysilicon or polycide layers.

Double polysilicon integrated circuit process

Abstract: In a double polysilicon integrated circuit processing method a first level polysilicon is used for FET gate fabrication, a second level is used for interconnection and both levels are used in the fabrication of analog capacitors over field oxide regions. By the invention, capacitors are also fabricated in the FET device well by implanting dopant through the second level polysilicon at the same time that dopant is implanted directly into other regions of the substrate to a greater depth and dopant level concentration so as to function as an FET source. The method is particularly adapted to fabricating DRAM memories.