Showing papers on "Polysilicon depletion effect published in 1992"

Polysilicon emitters for bipolar transistors: a review and re-evaluation of theory and experiment

Abstract: A critical review is presented of the theories proposed in the literature to explain the current gain enhancement of polysilicon emitter bipolar transistors. From these theories a simplified analytical formulation is chosen which models the blocking properties of the interface, including tunneling through the interfacial oxide, reduced grain boundary mobility at the polysilicon/silicon interface, and the potential barrier created by segregated dopant, which can all give rise to an enhanced current gain. Also modeled are the mechanisms which limit the extent of any gain enhancement, such as recombination in the single-crystal emitter, in the bulk of the polysilicon, and at the polysilicon/silicon interface. This model is then applied in an original manner to a selection of experimental data in an effort to identify the dominant current gain mechanisms in polysilicon emitter transistors as a function of a given set of fabrication conditions. >

Polysilicon as a material for microsensor applications

Abstract: Important characteristics of boron-doped LPCVD polysilicon layers with regard to sensor applications are presented. Properties such as the resistivity, temperature coefficient of the resistance, gauge factor and long-term stability are described. A pressure sensor utilizing polysilicon piezoresistors with a measurement range of 1 bar and a sensitivity of roughly 11 mV/V FS, a laser-trimmed polysilicon temperature sensor with a sensitivity of −3.4 × 10 −3 K −1 and non-linearity of less than 0.5% and a pressure sensor with polysilicon-based on-chip calibration and temperature compensation are described.

Low temperature plasma oxidation process

Abstract: A process for forming a thin film on a surface of a semiconductor device. The process involves formation of a silicon dioxide film by plasma enhanced thermal oxidation, employing a mixture of ozone and oxygen which are generated separately from the reactor chamber in a volume ratio of about 1-10/1, preferably about 5-7/1, at a temperature generally below 440° C., preferably about 350°-400° C. The process is used to form sidewall oxide spacers on polysilicon gates for field effect transistors. A relatively fast oxidation rate is achieved at a temperature significantly below that employed in conventional oxidation processes, and this serves to reduce dopant diffusion from the polysilicon. In addition, the resulting film demonstrates low stress with good conformal step coverage of the polysilicon gates. Another use of the process is to grow thin gate oxides and oxide-nitride-oxide with a thickness of less than 100Å. An oxide film of uniform thickness is formed by controlling the temperature, RF power, exposure time and oxygen/ozone ratio for thin gate oxide (<100Å) application in ULSI FET fabrication.

Performance of thin-film transistors on polysilicon films grown by low-pressure chemical vapor deposition at various pressures

Abstract: Defect properties of undoped low-pressure chemical-vapor-deposited (LPCVD) polysilicon films have been investigated by capacitance techniques on a simple metal-oxide-semiconductor (MOS) capacitor structure. The results show that the effective density of bulk and interface trap states is almost independent of the deposition pressure. After reducing the polysilicon film thickness by etching, although the grain size decreases due to the columnar mode of growth at low pressures, the trap states density reduces significantly. This finding could be explained by the hypothesis that, during the growth of the material, impurities are segregated at the film surface by fast diffusion through the grain boundaries. The transport properties of 0.5- mu m-thick polysilicon films deposited at a pressure ranging from 100 to 0.5 mtorr were evaluated from measurements on thin-film transistors (TFTs). The results demonstrate that at high pressures the grain boundaries and at low pressures the polysilicon-SiO/sub 2/ interface roughness scattering are the main factors in determining the transistor performance. >

Method of manufacturing polysilicon film including recrystallization of an amorphous film

Abstract: A method of fabricating a polysilicon film whose crystal grain size can be controlled in a wide range and which has a large surface area and an application thereof to a DRAM are disclosed. In polycrystallizing an amorphous silicon film having a substantially clean surface, nucleation and crystal growth are performed under different conditions. With this method, crystal grain density and crystal grain size can be controlled easily, causing a polysilicon film having finer grains to be formed concomitant with reduction of capacitor area due to increase of integration density of DRAM.

Polysilicon TFT circuit design and performance

Abstract: Both n- and p-channel polysilicon TFTs can be fabricated, allowing CMOS circuit techniques to be used. However, TFT characteristics are poor in comparison to conventional single-crystal MOSFETs, and relatively coarse design rules must be used to be compatible with processing on large-area glass plates. The authors examine these issues and describe the performance of a range of digital and analog circuit elements built using polysilicon TFTs. Digital circuit speeds in excess of 20 MHz are reported, along with operational amplifiers with over 80 dB of gain and more than 1-MHz unity-gain frequency. Several polysilicon TFT switched-capacitor circuits are also reported and shown to have adequate linearity, output swing, and settling time to form integrated data line drivers on an active-matrix liquid crystal display. >

Process for fabricating multiple pillars inside a dram trench for increased capacitor surface

Abstract: A method is disclosed for fabricating a DRAM trench capacitor with multiple-pillars inside the trench for increased surface area. A thin pad oxide of a few tens of nonometers is grown on a silicon substrate. A layer of silicon nitride is deposited and another layer of oxide is then deposited. This provides the ONO stack. Then a layer of polysilicon, a layer of nitride, and a layer of large-grained polysilicon are deposited sequentially. Then, a trench is defined by a lithographic mask and the exposed large-grained polysilicon is etched in CF4. Since CF4 etches the polysilicon and nitride 20 at almost the same rates, the topographical features existed in the polysilicon layer is copied to the nitride layer. The nitride layer is partially etched. The RIE etching gas is then changed to a mixture of HBR, SiF4, Helium, and NF3 which gives a very directional polysilicon etching with a good selectivity to nitride and a very high selectivity to oxide. Consequently, the topographical features on the nitride layer is enhanced and is transferred to the polysilicon layer which is used as a mask to etch the oxide nitride and pad oxide to form pillars.

Surface micromachined polysilicon accelerometer

Abstract: A surfaced micromachined polysilicon accelerometer is designed and manufactured. The sensing element represents a differential capacitor comprised of three polysilicon layers. The structure is made such that the seismic mass (polysilicon layer 2) is movable while the other polysilicon layers (layers 1 and 3) are nonmovable (fixed). The seismic mass is centered between the two fixed layers, thereby creating a differential capacitance: the bottom capacitance being formed between polysilicon layers 1 and 2, and the top capacitance being formed between polysilicon layers 2 and 3. The sensitive axis of the structure is in the direction perpendicular to the surface of the substrate. The device can be used with a signal processing circuit configured as an open loop system to achieve a sensitivity of 0.35 mV/g/V. >

Identification of perimeter depletion and emitter plug effects in deep-submicrometer, shallow-junction polysilicon emitter bipolar transistors

Abstract: Two new types of narrow-emitter effects are identified in shallow and narrow-junction polysilicon emitter bipolar transistors. These effects result from a lower doping concentration close to the emitter perimeter of large devices (perimeter depletion effect) or in very-narrow-emitter devices where the polysilicon plugs up the emitter window (emitter plug effect). The consequence is a locally shallower emitter junction which causes a reduced collector current density and a nonideal base current due to a partial overlap of the emitter-base space-charge region with the poly/monosilicon interface. The nonuniform doping in the polysilicon is verified by energy-dispersive X-ray spectroscopy (EDX) measurements. Electrical measurements give a clear indication of the emitter plug effect for two different self-aligned transistor structures, and further evidence is given by a comparison of various poly emitter processes. >

Novel polysilicon/TiN stacked-gate structure for fully-depleted SOI/CMOS

Abstract: Fully-depleted SOI/CMOS transistors were fabricated using titanium-nitride (TiN) gates with near midgap work-function in order to optimize the p- and n-channel threshold voltages for operation at low supply voltage. To simplify the process as well as to minimize the strain, a novel gate structure was used in which a thick polysilicon (300 nm) was stacked on a thin TiN layer ( >

Method for fabricating stacked capacitors with increased capacitance in a DRAM cell

Abstract: A method is described for fabricating a dynamic random access memory having a high capacitance stacked capacitor. Relatively thick field oxide areas are selectively formed on the surface of a semiconductor substrate while leaving device areas for fabrication of field effect devices. Gate structures and associated source/drain structures are formed within the device areas. A first silicon oxide layer is formed over the device and field oxide areas. The stacked capacitors are now formed by first depositing a thick second polysilicon layer oven the device and field oxide areas. Openings are formed to the desired source/drain structures by etching through the second oxide, second polysilicon, and first oxide layers. Cavities are formed between the first and second oxide layers by laterally etching the second polysilicon layer. A third polysilicon layer is deposited over the device and field oxide areas. The second and third polysilicon layers and the first and second oxide layers are patterned so as to have their remaining portions over the planned capacitor areas. The layers are etched leaving the third polysilicon layer as the bottom storage node electrode contacting the source/drain structures. The remaining second and third polysilicon layers form the storage node of the capacitor. A capacitor dielectric layer is formed over the bottom electrode polysilicon layer. A contact polysilicon layer is deposited as the top plate electrode and the contact polysilicon layer and the dielectric layer are patterned to complete the stacked capacitor.

Analysis of current voltage characteristics of low-temperature-processed polysilicon thin-film transistors

Abstract: The relationship between device performance and trap state density in polysilicon films was investigated. The density in the silicon energy gap was obtained by fitting the calculated on-state current versus gate voltage curve to the measured one for low-temperature ( >

A stacked CMOS SRAM cell with polysilicon transistor load

Abstract: A CMOS SRAM memory cell, and a method of making the same, is disclosed. The disclosed cell is configured as cross-coupled CMOS inverters, with the n-channel pull-down transistors in bulk, and with the p-channel load devices being accumulation mode p-channel transistors in a thin polysilicon film. The cross-coupling connection is made by way of an intermediate (12b) layer, which may include polysilicon at its top surface for performance enhancement, each of which makes contact to the drain region of an n-channel transistor, and to the opposite gate (86) electrode, via a buried contact. The intermediate layer also serves as the gate for the thin-film p-channel transistor, which has its channel region overlying the intermediate (12b) layer. The p-channel transistors may be formed so as to overlie part of the n-channel transistor in its inverter, thus reducing active chip area required for implementation of the memory cell.

Formation of vertical polysilicon resistor having a nitride sidewall for small static RAM cell

Abstract: A new method of forming a polysilicon resistor is achieved. Polysilicon gate structures and source/drain regions are formed in and on a semiconductor substrate. A passivation layer is formed overlying the gate structures. A contact window is opened to the drain portion of the source/drain region. A resistor is formed within the contact window as follows. A nitride layer is deposited over the passivation layer and within the contact window. The nitride layer is etched back to form nitride sidewalls within the contact window. A layer of polysilicon is deposited over the passivation layer and within the contact window. The polysilicon layer is etched back to leave the polysilicon only within the contact opening completing formation of the resistor. A second contact window is opened to the source portion of the source/drain region. A barrier metal layer is deposited over the passivation layer, over the resistor, and within the second contact window. A metal layer is deposited over the barrier metal layer and the metal interconnection of the integrated circuit is completed.

Method of making memory cell capacitor

Abstract: A method for making a memory cell capacitor is disclosed. Steps in accordance with present invention are: (1) forming a capacitor node contact hole after making necessary elements in a semiconductor substrate by depositing an insulation layer and etching a predetermined portion of the insulating layer by a photolithographic process; (2) depositing a doped polysilicon layer, thereby making a contact for connecting the capacitor electrode and a source/drain region in the semiconductor substrate; (3) depositing a silicon nitride layer and a first silicon oxide layer, and opening a window by a photolithographic process in the first silicon nitride layer and the silicon oxide layer at a position where the capacitor storage electrode is to be formed; (4) depositing a hemispherical polysilicon layer having peaks and valleys on the exposed surfaces of the polysilicon layer, the silicon nitride layer, and the first silicon oxide layer; (5) depositing a second oxide layer and etching back the second silicon oxide layer so that it selectively remains in the valleys of the hemispherical polysilicon layer; (6) forming a plurality of polysilicon projections by dry etching the hemispherical polysilicon layer and the polysilicon layer using the remaining portions of the second silicon oxide layer and the first silicon oxide layer as a mask; (7) removing the first and second silicon oxide layers by a wet etching process; (8) depositing a polyimide layer and etching back the polyimide layer so as to expose the surface of the silicon nitride layer; and (9) forming a capacitor storage electrode by removing the silicon nitride layer by a wet etching process, etching the polysilicon layer by using the polyimide layer as a mask, and removing the polyimide layer. In step (2), the doped polysilicon layer may be deposited to a thickness of about 2000 Å or more by applying a LPCVD process at a temperature of about 500° C. or more.

Method of manufacturing a fully planarized MOSFET and resulting structure

Abstract: A method is disclosed for forming MOSFET devices on a semiconductor substrate including steps of depositing layers of polysilicon, dielectric, and polysilicon again. Each polysilicon layer is planarized after it is deposited. The dielectric layer is patterned and etched to delineate active regions and interconnect grooves. After the second polysilicon layer is planarized, the material in the active region is patterned and etched to form a gate and source and drain areas. The appropriate areas of the active region are doped as necessary to form the source and drain.

Method of making flash memory cell

Abstract: The present invention relates to a flash EEPROM cell using polysilicon-to-polysilicon hot electron emission to erase the memory contents of the cell. Exemplary embodiments include a side gate, a control gate, a floating gate and source and drain regions. Appropriate biasing of these gates and source and drain regions controls the electron population of the floating gate. The memory cells may be of either the double polysilicon or triple polysilicon variety. Peripheral transistors are formed from a last formed polysilicon layer to avoid degrading the peripheral transistors.

Method of forming local etch stop landing pads for simultaneous, self-aligned dry etching of contact vias with various depths

Abstract: The present invention introduces the use of "local" etch stop layers having highly selective etch characteristics vis-a-vis insulating layers into which the contact/vias are etched. Any kind of conducting material which possesses etch selectivity to an insulator such as oxide (i.e. doped polysilicon, tungsten, tungsten silicide, titanium, titanium silicide, titanium nitride and the like) may be used and the process flow described herein uses conductively doped polysilicon as an example to accomplish this task without the need to add any extra photo or mask step to a conventional dynamic random access memory (DRAM) process flow and with the addition of a minimal number of deposition and etch steps. During a first masking step to open a contact, a subsequent etch opens up the P-channel gate area to thin down the underlying oxide. Polysilicon is then deposited which is followed by formation of an oxide. During a second masking step the oxide is etched and the polysilicon is etched thereby patterning the polysilicon and creating exposed polysilicon sidewalls. Dielectric isolation is then provided for the polysilicon sidewalls. In a first embodiment nitride spacers are then formed from a blanket layer of nitride which also results in nitride fillers about the polysilicon sidewalls. In a second embodiment the polysilicon sidewalls are oxidized thereby eliminating the steps for deposition and formation of nitride spacers. Next an etch stop layer of conductively doped polysilicon is deposited and covered with oxide. A third mask step allows a following etch to open local landing pads around future buried contact locations as well as define P-channel transistor gates.

Semiconductor device of MOS structure having p-type gate electrode

Abstract: A semiconductor device of a MOS structure having a p-type gate electrode has a gate electrode including at least two layers consisting of a boron-doped polysilicon layer and a polysilicon layer doped with boron and an inert material. This inert material is nitrogen or carbon.

Reverse polysilicon CMOS fabrication

Abstract: A CMOS integrated circuit such as a DRAM is fabricated, in which a first layer of polysilicon is used to form transistor gates, and capacitor cell plates are formed from a second polysilicon layer. N-wells are first formed, followed by initial oxide. The application of the CMOS process to the reverse poly technique provides enhanced alignment of critical transistor gates and permits the use of less mask steps in fabricating the CMOS circuit.

A study on the physical mechanism in the recovery of gate capacitance to C/sub ox/ in implanted polysilicon MOS structures

Abstract: The anomalous CV characteristics of MOS capacitor structures with implanted n/sup +/ polysilicon gate and p-type silicon substrate are studied through physical device simulation and experimental characterization over a wide range of frequencies and temperatures ranging from 100 to 250 K. It is shown that this anomalous CV behavior can be fully explained by the depletion of electrons and the formation of a hole inversion layer in the polysilicon gate due to energy band bending. The use of transistor structures for characterizing the polysilicon gate electrode is proposed. The results suggest thermal generation rather than impact ionization to be the dominant physical mechanism in supplying holes required by the inversion layer at the polysilicon-SiO/sub 2/ interface. This result also implies that hot-hole injection from the polysilicon gate into the SiO/sub 2/ gate dielectric should not present a serious problem in device reliability. >

Method of increasing capacitance of polycrystalline silicon devices by surface roughening and polycrystalline silicon devices

Abstract: A method of forming an electrically conductive polysilicon capacitor plate on a semiconductor substrate includes: a) providing a first layer of conductively doped polysilicon atop a semiconductor substrate to a first selected thickness; b) providing a thin layer of oxide atop the first polysilicon layer to a thickness of from about 2 Angstroms to about 30 Angstroms, the thin oxide layer having an outwardly exposed surface; and c) providing a second layer of conductively doped polysilicon having an outer exposed surface over the outwardly exposed thin oxide surface, the first polysilicon layer being electrically conductive with the second polysilicon layer through the thin layer of oxide, the second polysilicon layer having a second thickness from about 500 Angstroms to about 700 Angstroms, the thin oxide layer reducing silicon atom mobility during polysilicon deposition to induce roughness into the outer exposed polysilicon surface. Preferably, the polysilicon deposition, doping, oxide growth, and subsequent polysilicon deposition is all conducted in a single furnace sequence without removing the wafers from the furnace. Such facilitates throughput, and minimizes exposure of the wafer to handling which could lead to fatal damage. It is also contemplated that selected materials other than oxide would be usable to reduce the surface mobility, and thereby induce roughness. The invention also includes an electrically conductive polysilicon capacitor plate.

Method of making a split floating gate EEPROM cell

Abstract: A split floating gate EEPROM memory cell formed in a P-type silicon substrate includes source and drain buried n+ diffusion regions formed in the silicon substrate to define a substrate channel region therebetween. A layer of floating gate oxide about 400Å thick is formed over the source and drain regions and over the channel region. The floating gate oxide includes a region of thin tunnel oxide about 80-100Å thick formed therein over the drain region. A floating gate is formed on the floating gate oxide to extend over the channel region and includes a portion that extends over the tunnel oxide. The floating gate comprises a first layer of polysilicon about 300-600Å thick, a silicon dioxide layer about 20-50Å thick formed on the first layer of polysilicon, and a second layer of polysilicon about 2000Å thick formed on the silicon dioxide layer. A layer of ONO is formed on the floating gate and a polysilicon control gate is formed on the layer of ONO.

Process of fabricating semiconductor integrated circuit having conductive strips used as resistor and gate electrode of component transistor

Abstract: In a process according to the present invention, a polysilicon gate electrode and a high resistive polysilicon strip are simultaneously patterned on an active area and on a thick field oxide film, respectively, and the gate electrode and the polysilicon strip are covered with thin silicon oxide films, respectively, then impurities being doped in the active area to form source and drain regions, then the thin silicon oxide film being removed from the gate electrode, then a refractory metal silicide film being formed on the gate electrode, however, the formation of the refractory metal silicide film does not affect the polysilicon strip, because the thin silicon oxide film is left thereon, which results in maintaining the polysilicon strip in the high resistivity and, accordingly, in that the polysilicon strip provides a resistor with a large resistance but occupies a small amount of area.

Vertical DMOS transistor built in an n-well MOS-based BiCMOS process

Abstract: An integrated circuit is provided wherein bipolar, CMOS and DMOS devices are merged together on one chip with fabrication taking place from a CMOS point of view rather than from a bipolar point of view as in the prior art and p-type epitaxial silicon is used as opposed to n-type epitaxial silicon in the prior art. The integrated circuit uses a P+ substrate upon which a P- epitaxial layer is formed. N+ buried regions isolate the DMOS, PMOS and NPN bipolar devices from the P-epitaxial layer. Each of the devices is formed in a N-well with a first level of polysilicon gate layer providing both the gate and masking for the backgate diffusion of the DMOS device and a sidewall oxide later formed on the first level gate layer to control the diffusion of the source and drain regions of the DMOS device to control channel length. A second level of polysilicon layer provides the gate structures for the CMOS devices as well as one plate of a capacitor. The second level of polysilicon acts as a mask for the source and drain region implants of the CMOS devices. A sidewall oxide later formed on the second polysilicon level further controls the channel lengths of the CMOS structures. A third level of polysilicon provides the second capacitor plate for the capacitor. The DMOS device is isolated from the remaining circuitry by the p-type epitaxial layer and the peripheral portion of the DMOS device is terminated by a PN junction, thereby avoiding the necessity of having a tapered field oxide.

Fabrication of transistor contacts

Abstract: The method of forming an integrated circuit field effect transistor having a gate electrode, source and drain elements with buried contacts to a silicon substrate. A gate silicon oxide layer is formed on the silicon substrate. An in-situ doped layer of polysilicon is formed over the gate silicon oxide layer. An opening is formed in the doped polysilicon layer and the silicon oxide layer to the silicon substrate at the location of the buried contacts. A layer of undoped polysilicon is deposited over the doped polysilicon layer and in the opening to the silicon substrate. Doping by ion implantation of the undoped polysilicon layer is done to form a doped polysilicon gate electrode/buried contact layer. The polysilicon gate electrode/buried contact layer is patterning and etching to form the gate electrode of said transistor and buried contact layer. The source and drain regions are implanted using said polysilicon gate electrode pattern as a mask. The structure is heated to form the buried contact to at least one of the source and drain regions. Alternatively, a contact to an existing device region within the substrate may be contacted using a similar multiple layer polysilicon method.

Hinged polysilicon structures with integrated CMOS TFTs

Abstract: The surface micromachining process described can produce a variety of microelectromechanical components, including CMOS thin film transistors and three dimensional polysilicon structures with large features and high detail in all three dimensions. Polysilicon structural elements are made with integrated hinges, which allow three dimensional structures to be erected out of the plane of the wafer. CMOS transistors are integrated directly in the structural thin films, and flexible polysilicon elements electrically connect the structures to the substrate. Some batch assembly of the structural elements has been demonstrated, and a first generation CAD system has been developed to model the structural half of the process. >

Non-volatile memory and method of manufacturing the same

Abstract: A non-volatile memory comprises an auxiliary gate (14) of polysilicon provided on a Si substrate having a gate insulating and a field oxidation film; a floating gate (92) which is provided on a side wall of the auxiliary gate (14) lying in an active region with a small piece of a first insulating film interposed between them and which is formed by etchback of useless part of a polysilicon side wall spacer; and a control gate (30) of polysilicon provided at least on the floating gate (92) including a second insulating film interposed between them; the floating gate (92) being formed in self-alignment to the control gate (30).

Method for forming bipolar transistor input protection

Abstract: A protective circuit for an input to a bipolar transistor (10) capable of operating in the microwave frequency range. In a first embodiment, a polysilicon diode (24) is connected across a base-emitter junction of the bipolar transistor (10). In a second embodiment, a polysilicon resistor (38) is connected in series with an emitter of the bipolar transistor (10), and the polysilicon diode (24) is connected across the series combination of the base-emitter junction and the polysilicon resistor (38). The layout of the transistor (10) and the islands of polysilicon (23, 25) housing the diode is critical since the bipolar transistor (10) is capable of operating in the microwave frequency range. In a first layout, an island of polysilicon (25) is centered between two transistor regions (47 and 48). In an exterior diode layout, a transistor region (51) is centered between two islands of polysilicon (23 and 25).

Method of making semiconductor device having polysilicon resistance element

Abstract: A polysilicon resistor element and a semiconductor device using the same are disclosed. The polysilicon resistor element has a resistive polysilicon film formed on a predetermined interlayer insulating film of a semiconductor chip. The resistive polysilicon film is covered by an insulating film having holes and high melting point metal films are formed in self-alignment to the holes. The high melting metal film constitutes one of lead portions of the polysilicon resistor element. A diffusion of the high melting point metal film due to heat treatment during fabrication, which causes an effective length of the resistor element, becomes negligible and reproducibility is improved.