Showing papers on "Pulse-width modulation published in 2020"

A Tutorial and Review Discussion of Modulation, Control and Tuning of High-Performance DC-DC Converters Based on Small-Signal and Large-Signal Approaches

Abstract: Many commercial controller implementations for dc-dc converters are based on pulse-width modulation (PWM) and small-signal analysis. Increasing switching frequencies, linked in part to wide bandgap devices, provide the opportunity to increase operating bandwidth and enhance performance. Fast processors and digital signal processing offer new computational techniques for power converter control. Conventional control techniques rarely make full use of operating capability. The objectives of this paper are to present an overview and link to literature on conventional modulation and control techniques for hard-switched dc-dc converters, identify performance limits associated with conventional small-signal-based design, discuss geometric control approaches, and compare strategies for control tuning. The discussion shows how current mode controls have alternative state feedback implementations, and describes unusual opportunities for large-signal control tuning. Considerations for minimum response time are described. Comparisons among tuning methods illustrate how geometric controls can achieve order of magnitude dynamic performance increases. The paper is intended as a baseline tutorial reference for future work on power converter control.

Low-Loss Integrated Inductor and Transformer Structure and Application in Regulated LLC Converter for 48-V Bus Converter

Abstract: In this article, an LLC converter using gallium nitride (GaN) transistors is proposed for a 48-V regulated and isolated bus converter. Compared with pulsewidth modulation (PWM)-based topologies, the soft switching capability of an LLC allows operation at very high frequencies. In addition, the size of the magnetic components is reduced without sacrificing the efficiency. In this article, a novel magnetic structure that integrates a matrix transformer and inductor with minimum winding and a single magnetic core is proposed, to allow a high-density and high-efficiency LLC converter design for a bus converter. A 40—60-V input and regulated 12-V output converter is developed to deliver a 1-kW output power in a quarter brick form factor. The designed converter can achieve a power density of 700 W/in3 with a maximum efficiency of 97.82% at half-load, dropping to 97.7% at full-load operation.

Topology and Control of a Four-Level ANPC Inverter

Abstract: Four-level hybrid-clamped inverter is a newly proposed topology that can operate under a wide voltage range without switches connected in series. However, when it is applied in medium voltage high power conversions, the flying capacitors in each phase will occupy a huge volume and a high switching frequency is required to restrain the voltage ripples. In order to overcome this drawback, a four-level active neutral-point clamped inverter is discussed in this paper, which consists of only six switches and no diodes or flying capacitors are required. In order to balance the neutral-point voltages under the full power factor and modulation index range, a capacitor voltage balance method based on carrier-overlapped pulsewidth modulation is proposed in this paper. The upper and lower dc-link capacitor voltages are balanced by zero-sequence voltage injection and the central dc-link capacitor voltage is balanced by adjusting the duty cycles of switching signals slightly. Simulation and experimental results are presented to confirm the validity of this method.

Design of Passive Common-Mode Attenuation Methods for Inverter-Fed Induction Motor Drive With Reduced Common-Mode Voltage PWM Technique

Abstract: This paper investigates the influence of active zero vector pulsewidth modulation (AZPWM-1) and space vector pulsewidth modulation (SVPWM) on the design of passive common-mode (CM) attenuation methods to reduce CM current and shaft voltage in inverter-fed V/f-controlled induction motor drives. The passive CM attenuation methods examined here are the CM choke, the CM electromagnetic interference (EMI) filter, and the CM transformer. The attenuation requirement of AZPWM-1 and SVPWM is identified to design the passive CM choke and EMI filter. Based on the attenuation requirement, the design guidelines are revisited for SVPWM, and design rules are proposed for AZPWM-1. However, the CM transformer is designed based on the step change in magnitude of CM voltage of both the pulsewidth modulations (PWMs). The limitations in design, regarding switching frequency and component size for each case, are also established. It is shown that to have a similar attenuation in the considered two PWM cases, AZPWM-1 requires smaller passive components compared to SVPWM. The proposed design guidelines are substantiated with experimental results on a 1.1-kW induction motor drive.

Highly Efficient Bidirectional Series-Resonant DC/DC Converter Over Wide Range of Battery Voltages

Abstract: This article introduces a highly efficient bidirectional resonant dc/dc converter over wide range of battery voltages for vehicle-to-grid (V2G) capable electric vehicles (EVs). It operates as a pulsewidth-modulation (PWM) full-bridge series-resonant converter in the forward direction and a half-bridge resonant boost converter in the backward direction. One advantage of the proposed converter is that it has a wide voltage gain range in the backward operation. Also, it requires only six active switches. To achieve high efficiency, SiC mosfet s are used for two bottom switches in the primary side, because only these switches suffer hard switching turn- off in both forward and backward directions. Since it operates with fixed-frequency and with PWM control, the magnetic components and passive filters can be optimally designed with respect to the volume and the loss. Thus, the proposed converter achieves low-cost, high-conversion ratio, and high efficiency over a wide range of battery voltages. Detailed analysis of the converter operation is presented along with the design procedure. A 3.3-kW/400-V prototype of the proposed converter has been built to operate for 250–415 V primary source voltages and tested to demonstrate its circuit design.

Design and Implementation of New Multilevel Inverter Topology for Trinary Sequence Using Unipolar Pulsewidth Modulation

Abstract: This paper proposes a new multilevel inverter (MLI) topology that utilizes trinary sequence for the dc sources. It gives maximum output voltage level with minimum dc source and switch count when compared to other sequences, such as symmetric, natural, binary, and quasi-linear. This is due to the fact that the trinary sequence generates of all additive and subtractive combinations of input dc levels in the output voltage waveform. The concept is implemented on a 9-level asymmetric MLI using only four active devices. Multicarrier unipolar pulsewidth modulation technique is adopted to create the switching pulses. Theoretical calculation of total harmonic distortion in both voltage and current waveforms has been performed using asymptotic time domain formula. These values are compared with simulation and experimental values for different modulation indices. Power loss calculation for proposed topology is discussed with appropriate mathematical equations.

Common-Mode Voltage Elimination for Dual Two-Level Inverter-Fed Asymmetrical Six-Phase PMSM

Abstract: The voltage-source inverter with pulsewidth modulation (PWM) is widely used in motor drive applications owing to the technical maturity and simplicity. However, the inverter operating in the discrete and impulse state generates the high-frequency common-mode voltage (CMV) in the neutral point terminal of stator winding, which induces the negative effects. This article proposes a CMV elimination modulation scheme for the dual two-level inverter-fed asymmetrical six-phase permanent magnet synchronous motor, which has two sets of three-phase windings spatially shifted by 30° electrical degrees. The modulation algorithm shifts the PWM signals with the designed end-to-end cyclic sequence, which can retain the zero-voltage vectors for each sub-CMV of dual three-phase windings and theoretically eliminate the total CMV for the motor drive system. The validation of the proposal is verified by simulations and experiments.

A Generalized Carrier-Overlapped PWM Method for Neutral-Point-Clamped Multilevel Converters

Abstract: The neutral-point voltage unbalance problem holds back the extensive application of neutral-point-clamped (NPC) multilevel converters with more than three voltage levels in industry. Traditional phase-disposition pulsewidth modulation (PDPWM) or nearest-three-vector (NTV) modulation cannot achieve the voltage balance over the full modulation indexes and load power factors when the voltage level is higher than three. To solve this problem, a novel generalized carrier-based PWM method, named carrier-overlapped PWM (COPWM), for NPC multilevel converters is proposed in this article, which is proven to satisfy the volt–second balance principle. With this modulation method, the average values of all the neutral-point currents are equal to zero in a fundamental period, and therefore, all the dc-link capacitor voltages can be naturally balanced in the ideal and steady-state conditions. In order to simplify its implementation, an equivalent multireference modulation method with only one triangular carrier is also derived. Simulation and experimental results on a five-level diode-clamped inverter are presented to verify the proposed modulation method.

Power Quality Performance Evaluation of Multilevel Inverter With Reduced Switching Devices and Minimum Standing Voltage

Abstract: Multilevel inverters (MLIs) have been extensively employed to improve the power quality of the photovoltaic (PV) systems. However, the need for large number of components, higher standing voltage, and high harmonic content in the output of a conventional MLI greatly affects the system efficiency. Asymmetrical MLIs have been therefore developed as a suitable alternative to address these issues. This article aims at developing such a hybrid asymmetrical structure suitable for PV application that has a high level per component ratio and minimum standing voltage. The proposed MLI is assembled using a reduced switch H-bridge-based (RSHB) MLI structure with n asymmetrical repeating units and different level doubling circuit (LDC) combinations. The two dc sources used in the repeating units are in the ratio of 1: n voltage ratio, and using n such units, the proposed MLI structures, i.e., PS1 and PS2 can synthesize 4 n + 5 and 4 n + 7 levels, respectively, at the output instead of 2 n + 3 levels with only RSHB MLI. Comparative analysis reveals that both PS1 and PS2 have fewer switches, low standing voltage, less power loss, and lower cost. A 3.9-kW standalone solar PV system is considered for performance evaluation of the PS1 structure applying both the selective harmonic elimination and carrier-based pulsewidth modulation control schemes. In light of this, dc-link voltage balancing and self-voltage balancing mechanism of the LDC are warranted. Extensive simulation of the proposed MLI is performed in MATLAB/Simulink platform under a change in modulation index, sudden load change, frequency change, and step change in solar insolation. Furthermore, theoretical and simulation findings are validated experimentally by performing similar tests on a prototype of the proposed 17-level MLI.

Nonisolated High Step-Up Soft-Switching DC–DC Converter With Interleaving and Dickson Switched-Capacitor Techniques

Abstract: In this article, a nonisolated high step-up soft-switching dc-dc converter is proposed, which is based on a hybrid structure comprising an interleaved boost converter and Dickson switched-capacitor (SC) networks. The high voltage gain can be achieved by the SC networks without an extremely large duty cycle, and the voltage stresses of all the active switches and diodes are kept at levels much lower than the output voltage. Compared with the traditional SC converters, the proposed converter can achieve continuous voltage regulation by the pulsewidth modulation (PWM) technique. The interleaving operation can reduce the input current ripple and improve the power capacity. Resonant inductors with small inductances are inserted into the SC networks to avoid the high current spikes that occur in the traditional SC converters. All the active switches can achieve zero-voltage switching (ZVS) turn-on. Some of the diodes can achieve zero-current switching (ZCS) turn-off, and the other diodes achieve reduced turn-off ${di/dt}$ rates. The operating principle and essential steady-state characteristics of the converter are analyzed in detail. Finally, a prototype converter with an input voltage of 25–40 V, an output voltage of 400 V, and a rated power of 1 kW is designed and implemented to verify the theoretical analysis.

Distributed Secondary Control for Current Sharing and Voltage Restoration in DC Microgrid

Abstract: Direct current (DC) microgrid is being increasingly investigated in modern power grid. An important issue in DC microgrid operation is to ensure proper current sharing among converters. While this has been addressed through droop control, the resulting voltage deviation in DC bus has to be compensated. To solve this problem, a new distributed secondary control scheme is presented in this paper for both current sharing and voltage restoration. A key part of the presented scheme is the integration of a new parameter ‘virtual voltage drop’ defined from droop gain and line resistance. Since the DC bus voltage is not required as a feedback signal, the proposed secondary control is simple and easy to design and implement. In addition, as the proposed scheme has no requirement for the loads, it can handle both resistance loads and constant power loads (CPLs). Simulations as well as experimental studies are carried out to demonstrate the effectiveness of the proposed scheme.

Reduced Switch Count Based Single Source 7L Boost Inverter Topology

Abstract: The new inverter topologies based on switched capacitor concept with voltage boosting ability are attractive for the low voltage applications. Such low voltage requirements allow a single-stage dc-ac power conversion, improving overall system performance, reliability and power density. This brief proposes a new multilevel inverter topology based on the switched-capacitor (SC) with a single source of dc voltage. The proposed topology is ideal for low voltage renewable energy applications. Seven-level (7L) output voltage is accomplished with triple voltage gain using two switched capacitors and 10 switches. Other major features of the proposed topology are self-voltage balancing of capacitor voltages, reduced number of switches with lower voltage stress and generation of negative voltage levels without using backend H-bridge. To show the advantages of the proposed topology, a detailed comparison with other similar topologies with seven-level single-source configuration has been accomplished in this brief. The proposed topology has been tested using the traditional level-shifted sinusoidal pulse width modulation (LS-PWM) technique. This brief includes various experimental results with different operating conditions to prove the performance of the proposed topology.

A new single‐phase cascaded multilevel inverter topology with reduced number of switches and voltage stress

Abstract: Int Trans Electr Energ Syst. 2019;e12191. https://doi.org/10.1002/2050-7038.12191 Summary Multilevel inverters have been the vital component for the power electronic systems and have been researched extensively to further enhance their performances in terms of topology and their control. In this paper, a new bidirectional single‐phase multilevel inverter module has been proposed with a reduced number of switches along with lower voltage stresses. The proposed module generates 17 levels at the output with 10 unidirectional switches along with four dc voltage sources with two varieties of dc voltage sources. Moreover, for a higher number of levels, the cascade connection of several modules has been discussed in this paper with three different methods for the selection of dc voltage sources. The proposed module has been compared with several similar topologies, which set the benchmark of the proposed one. The operation and performance of the proposed module have been validated through several simulation and experimental results with different types of load considering a change of modulation index.

Grid-Voltage Sensorless Model Predictive Control of Three-Phase PWM Rectifier Under Unbalanced and Distorted Grid Voltages

Abstract: The sensors in a three-phase pulse width modulation (PWM) rectifier control system are the basis of high-performance methods. Line voltage sensors are utilized to obtain information about the grid voltage amplitude and phase. To eliminate the grid voltage sensors and to decrease the cost of PWM rectifier control systems, various grid-voltage sensorless methods have been developed. In this article, a virtual-flux-based grid voltage estimation method is utilized in the model predictive control (MPC) of a PWM rectifier. The extended reactive power is introduced in the proposed MPC method; the MPC is then able to realize the control targets of eliminating input-side power oscillations and ensuring sinusoidal currents under unbalanced network conditions without any power compensation terms. The cascaded delayed signal cancellation (CDSC) method is applied to obtain the fundamental rectifier voltages in the virtual flux-based grid-voltage sensorless method. The proposed method can operate under unbalanced and distorted network conditions. Moreover, a startup current suppression method is applied in this method to avoid over-currents during the startup process. Experimental tests are performed to verify the effectiveness of the proposed method.

Nonisolated Multiport Converters Based on Integration of PWM Converter and Phase-Shift-Switched Capacitor Converter

Abstract: Photovoltaic (PV) systems having rechargeable batteries are prone to be complex and costly because multiple converters are necessary to individually regulate a load, PV panel, and battery. This paper proposes novel nonisolated multiport converters (MPCs) integrating a bidirectional pulsewidth modulation (PWM) converter and phase-shift-switched capacitor converter (PS-SCC) for standalone PV systems. A PWM converter and PS-SCC are integrated by reducing the total switch count, realizing the simplified system and circuit. In the proposed MPCs, two control freedoms of duty cycle and phase shift angle are manipulated to individually regulate the load, PV panel, and/or battery. The detailed operation analysis was performed to mathematically derive gain characteristics and zero voltage switching operation boundaries. For the battery discharging mode, in which the PV panel is not available and the MPC behaves as a single-input–single-output converter with two control freedoms available, the optimized control scheme achieving the lowest rms current is also proposed to maximize power conversion efficiencies. Various kinds of experimental verification tests using a 200-W prototype were performed to verify the theoretical analysis and to demonstrate the performance of the proposed MPC.

The essence of the little box challenge-part A: Key design challenges & solutions

Abstract: In order to expedite the development of power electronic systems towards higher power density and efficiency at a lower cost of implementation, Google and IEEE initiated the Google Little Box Challenge (GLBC) aiming for the worldwide smallest 2 kVA / 450 V DC / 230 V AC single-phase PV inverter with η > 95 % CEC weighted efficiency and an air-cooled case temperature of less than 60 °C by using latest power semiconductor technology and innovative topological concepts. This paper, i.e., Part A of a discussion of The Essence of the Little Box Challenge, documents all important RD Part B is intended to convey the main findings and lessons learned from the participation in the GLBC. First, the key technical challenges of the GLBC are discussed and the technologies and concepts selected by the authors among different options are described in detail. Relevant design considerations, such as constant frequency pulse width modulation (PWM) or triangular current mode (TCM) operation of the bridge-legs, selection of power semiconductor technology, interleaving of bridge-legs, sizing of the power buffer capacitor, limitation of ground/leakage currents, etc., to achieve an ultra-compact implementation are discussed. Based on this overview, two promising inverter concepts to tackle the GLBC, (i) an H-bridge based inverter with DC-link referenced output filter and (ii) a DC/|AC| buck-stage with series-connected low-frequency (LF) |AC|/AC unfolder inverter, are then analyzed in detail. Based on the results of a multi-objective ηρ-Pareto optimization, a comparative evaluation of the performance in terms of efficiency (η) and power density (ρ) of the two considered inverter concepts is provided. It is shown that with the DC/|AC| buck-stage and |AC|/AC H-bridge unfolder inverter operated with 140 kHz PWM a power density of 14.7 kW/dm 3 (240 W/in 3 ) with a maximum efficiency of 98.1% at 2 kW output power can be achieved. These claims are then verified in Part B by means of experimental results obtained from prototype realizations and compared to the achievements of other GLBC finalists. The conclusions are of general importance and are providing key guidelines for the future development of ultra-compact power electronic converters.

Dual input switched-capacitor-based single-phase hybrid boost multilevel inverter topology with reduced number of components

Abstract: A new switched-capacitor-based topology with features of boosting and self-voltage balancing of the capacitor has been proposed in this study. The proposed multilevel inverter topology uses two isolated dc voltage sources with a switched-capacitor to produce 11 levels across the load. In this study, two different modes of the selection of dc voltage sources have been discussed for the proposed topology. Furthermore, the generalised structure of the proposed boost topology has also been discussed. Quantitative comparison with several topologies has been carried out to set the benchmark of the proposed topology. Selective harmonic elimination pulse width modulation technique has been adopted to improve the performance of the suggested topology. The power loss analysis of the proposed topology gives the maximum efficiency of 96.5% at the output power of 100 W and has an efficiency value of 95.3% at the output power of 500 W. The proposed topology has been simulated using PLECS and the simulation results have been verifying using an experimental prototype. The proposed topology has been tested for the different types of load and changes in the modulation index. The experimental results have verified the feasibility of the proposed topology.

Analysis of a synergetically controlled two-stage three-phase DC/AC buck-boost converter

Abstract: Three-phase DC/AC power electronics converter systems used in battery-powered variable-speed drive systems or employed in three-phase mains-supplied battery charger applications usually feature two power conversion stages. In both cases, typically a DC/DC stage is attached to a three-phase DC/AC stage in order to enable buck-boost functionality and/or a wide input-output voltage operating range. However, a two-stage solution leads to a high number of switched bridge-legs and hence, results in high switching losses, if the degrees of freedom available for controlling the overall system are not utilised. If the DC/DC stage is used to vary the DC link voltage with six times the AC-side frequency, a pulse width modulation (PWM) of always only one phase of the DC/AC stage is sufficient to achieve three-phase sinusoidal output currents. The clamping of two phases (denoted as 1/3 PWM) leads to a drastic reduction of the DC/AC stage switching losses, which is further accentuated by a DC link voltage which is lower than for the conventional modulation schemes. This paper details the operating principle of a three-phase buck-boost converter system using 1/3 PWM and outlines an appropriate control system design. Subsequently, the switching losses and the voltage/current stresses on the converter components are analytically derived. There, a more than 66% reduction of the DC/AC stage switching losses is calculated without any increase of the stress on the remaining converter components. The theoretical considerations are finally verified on a hardware demonstrator, where the proposed modulation strategy is experimentally compared against several conventional modulation techniques and its clear performance advantages are validated.

An Interleaved Secondary-Side Modulated LLC Resonant Converter for Wide Output Range Applications

Abstract: In this paper, an LLC type converter with two interleaved pulsewidth modulation (PWM) rectifiers is proposed. Compared with the conventional LLC converter, it achieves a wide voltage regulation range independent of load. In the proposed structure, each secondary-side PWM rectifier can operate individually. With the interleaving technique and shared primary-side switching network, the circuit secondary-side current stress is halved and the primary-side current stress is largely reduced. Besides, the filter capacitor requirement is reduced. Therefore, the proposed structure is a good option for medium/high power wide output range applications. The symmetrical LLC resonant tanks always operate at the resonant frequency, which marks the optimal operation point of the LLC resonant tank. Therefore, the conduction loss is effectively mitigated. In the proposed converter, zero-voltage turning- on (ZVS) of the primary-side MOSFETs can be ensured and is independent of the load. Moreover, the turning- off currents of the primary-side MOSFETs are small and are also load independent. This brings the benefits of minimized circulating current and negligible turning- off loss and no MOSFET turning- off voltage spike. The secondary-side auxiliary MOSFETs turn- on with ZVS and rectifying diodes turn- off with limited di / dt. Topological analysis and experimental results of a 1.3 kW/100 kHz prototype generating 230–440 V output from 390-V input are presented. The prototype demonstrates 97.31% peak efficiency and good performance over a wide output range.

An Extensive Review of Multilevel Inverters Based on Their Multifaceted Structural Configuration, Triggering Methods and Applications

Abstract: Power electronic converters are used to transform one form of energy to another. They are classified into four types depending upon the nature of the input and output voltages. The inverter is one among those types; it converts direct electrical current into alternating electrical current at desired frequency. Conventional types of inverters are capable of producing voltage at the output terminal that can only switch between two levels. The range of output voltage generated at the output is low when they are used for high power applications. To improve the voltage profile and efficiency of the overall system, multilevel inverters (MLIs) are introduced. In multilevel inverters the voltage at the output terminal is generated from several DC voltage levels fed at its input. The generated output is more appropriate to a sine wave and the dv/dt rating is also less leading to the reduction in EMI. Though they possess many advantages compared to the conventional inverters, the structural complexity and triggering techniques involved in designing multilevel inverters are high. Many studies are being carried out in defining new topologies of MLI with reduced switch as well as with the implementation of different PWM techniques. This paper will provide an extensive review on variety of MLI configurations based on the parameters such as the number of switches, switching techniques, symmetric, asymmetric, hybrid topologies, configurations based on applications, THD and power quality.

IPMSM Sensorless Control Using High-Frequency Voltage Injection Method With Random Switching Frequency for Audible Noise Improvement

Abstract: A high-frequency (HF) voltage injection method can accurately estimate the rotor position of an interior permanent magnet synchronous motor at low speed. However, the fixed injection frequency for the traditional HF voltage injection method will produce a loud audible noise that limits the actual application of HF voltage injection method. In order to reduce the audible noise, a novel HF square-wave voltage injection method with the random switching frequency is proposed in this article. The frequency of the injected HF voltage varies with the random switching frequency, so it can effectively spread power spectrum caused by HF current and pulsewidth modulation (PWM), which will effectively reduce the audible noise caused by the HF current and PWM. Additionally, the power spectral density of the HF current based on the proposed method is analyzed to verify the effectiveness in reducing audible noise. Then, a corresponding demodulation method for induced HF current is presented. Finally, the experimental results show that the proposed method has continuous spectra and the audible noises can be suppressed significantly.

A Novel Scalar PWM Method to Reduce Leakage Current in Three-Phase Two-Level Transformerless Grid-Connected VSIs

Abstract: The advancement in modulation strategies brings emergent solutions to suppress the leakage current in three-phase two-level transformerless grid-connected voltage source inverters (VSIs). However, most of the techniques are analyzed based on reduced common-mode voltage pulsewidth modulation (PWM) in motor drivers but fail to satisfy the specific requirement of grid-connected applications, such as wider power factor operation and lesser current distortion. To overcome such substantial drawbacks, this paper proposes a novel scalar PWM method for transformerless grid-connected VSIs. First, presented through a generalized scalar approach with unified zero-sequence voltage generation, the method is simple to implement and favored in practice. Besides, systematic and comprehensive mathematical analysis is illustrated to exhibit the validity of implemented method in reducing leakage current and shows its advantages over whole power factor range in terms of dc-link current harmonic, output current quality, and switching losses. Finally, simulations and experimental results are carried out to verify the effectiveness and superiority of the proposed method.

An Improved Modulation Technique With Minimum Switching Actions Within One PWM Cycle for Open-End Winding PMSM System With Isolated DC Bus

Abstract: Due to the application of dual inverters in the structure of open-end winding permanent-magnet synchronous machine system with isolated dc bus, the double number of switching devices are employed and thus the switching actions within one pulsewidth modulation (PWM) period are relatively high. To reduce the switching actions, an improved modulation technique is proposed in this letter. In the proposed technique, the reference voltages in the synchronous coordinate system are transferred to the three-phase stationary frame through Park transformation and thus the duration time corresponding to the three-phase windings can be directly obtained. On this basis, by synchronously adjusting the duration time of three phases, the maximum one can be adjusted to be the control period while their resultant voltage remains constant. Furthermore, the switching actions are assigned to the switching devices based on the polarity of duration time for each phase, with the principle of keeping the switching device on one side clamped. The novelty of the proposed technique is that it can be universally applied to minimize the number of switching actions within one PWM cycle for any kind of voltage ratio of the system without sector identification. The experimental validation of the proposed scheme is given to validate its effectiveness.

Multisampling Method for Single-Phase Grid-Connected Cascaded H-Bridge Inverters

Abstract: This article proposes a multisampling method for single-phase grid-connected cascaded H-bridge (CHB) multilevel inverters with the phase-shifted carrier pulsewidth modulation in order to reduce the time delay involved in the control loop and increase the control bandwidth. In this method, the controlled variables are sampled not only at the peak and the valley of all triangular carriers, but also at the intersection points of all phase-shifted carriers and inverted ones, which enables a minimum unity sampling interval without detecting the current ripple caused by the switching action and breaking the voltage-second balance in the modulation process. The bandwidth of the current control loop based on the proposed sampling method is illustrated and compared to other traditional sampling methods. The analysis shows that the system effectively reduces the time delay involved in the control loop and improves the bandwidth of the control loop. Finally, a downscale test platform of the single-phase grid-connected CHB multilevel inverter with an inductance ( L )-filter is built to verify the effectiveness of the proposed method.

An Optimized Carrier-Based PWM Method and Voltage Balancing Control for Five-Level ANPC Converters

Abstract: Five-level active neutral-point clamped (5L-ANPC) converter is an attractive topology, which is suitable for medium-voltage high-power conversions. Both phase-disposition pulsewidth modulation (PDPWM) and phase-shifted PWM (PSPWM) can be used to control this converter. PDPWM has the best harmonic characteristics, but the conduction and switching losses are not uniformly distributed. Although PSPWM has the natural voltage balance ability for flying-capacitor cells, its quality of line voltage is much worse than PDPWM. In order to combine the advantages of these two modulation methods, an optimized carrier-based PWM method for 5L-ANPC converters is proposed in this article, which features the same harmonic performance with PDPWM and the same control characteristics with PSPWM. An optimized neutral-point potential balance method is also proposed, which can make a tradeoff between the neutral-point potential balancing and the harmonic performance. Simulation and experimental results demonstrated the feasibility of this method.

A 5-Level Inverter Scheme Using Single DC Link With Reduced Number of Floating Capacitors and Switches for Open-End IM Drives

Abstract: This paper presents a 5-level inverter topology for open-end induction motor drives by using a single dc source. The open stator windings of the drive are supplied with a 3-level flying capacitor inverter from one end and capacitor-fed 2-level inverter from another end. The voltage ratio of the dc link to the capacitor in 2-level inverter is maintained at 4:1 ratio to generate five-level voltage output. The capacitor in 2-level inverter is balanced by the switching redundant vector combinations from both the inverters while the floating capacitors in the 3-level inverter are balanced by using redundant switching states. The proposed topology gives 5-level operation with less number of floating capacitors and power semiconductor switches compared to other existing topologies. Also, the balancing of the capacitors is independent of load power factor and modulation index. Further, the generalization of the proposed dual inverter scheme for any n -level inverter is also included in this paper. The experimental results and required analysis are also presented to validate the inverter scheme.

Reconfigurable Hybrid Energy Storage System for an Electric Vehicle DC–AC Inverter

Abstract: Hybrid energy storage systems using battery packs and super capacitor (SC) banks are gaining considerable attraction in electric vehicle (EV) applications. In this article, a new modular reconfigurable multisource inverter (MSI) is proposed for active control of energy storage systems in EV applications. Unlike the conventional approaches, which use massive high-power dc–dc converters with bulk magnetic elements for combining SC banks and battery packs, the new approach utilizing the MSI offers magnetic-less structures. This reduces the weight and volume of the power electronics interface and offers simple control. Along with the proposed MSI, a space vector modulation technique and a deterministic state of charge (SOC) controller are also introduced for the control of the switching actions and operation of the SC bank. Simulations using MATLAB/Simulink and experimental results on a scaled down lab prototype are studied to assess the concepts.

Vibration Reduction for Dual-Branch Three-Phase Permanent Magnet Synchronous Motor With Carrier Phase-Shift Technique

Abstract: In motor drive system, ear-piercing acoustic noise caused by high-frequency vibration from motor becomes unacceptable in sensitive environments, due to the application of pulsewidth modulation (PWM) and consideration of switching losses. In this paper, a novel method which associates a presented dual three-phase permanent magnet synchronous motor (PMSM) called dual-branch three-phase PMSM with carrier phase-shift technique is implemented to completely reduce odd-order PWM frequency vibration. The proposed motor has two no phase-shift three-phase windings, whose coils wind on the same teeth; it is driven by paralleled inverters with magnetically coupled inductors. With carrier phase shifting $\pi $ , the odd-order carrier frequency current harmonics with the identical amplitude in two windings are opposite in phase, and therefore the produced magneto-motive-force (MMF) harmonics in the air gap offset with each other. The experimental results are provided to verify the validity of the proposed method in vibration reduction. Compared with the previous work of vibration reduction for dual three-phase PMSMs, the proposed method can achieve total elimination of odd-order PWM frequency vibration.

Neuromorphic Computing Using NAND Flash Memory Architecture With Pulse Width Modulation Scheme.

Abstract: A novel operation scheme is proposed for high-density and highly robust neuromorphic computing based on NAND flash memory architecture. Analog input is represented with time-encoded input pulse by pulse width modulation (PWM) circuit, and 4-bit synaptic weight is represented with adjustable conductance of NAND cells. Pulse width modulation scheme for analog input value and proposed operation scheme is suitably applicable to the conventional NAND flash architecture to implement a neuromorphic system without additional change of memory architecture. Saturated current-voltage characteristic of NAND cells eliminates the effect of serial resistance of adjacent cells where a pass bias is applied in a synaptic string and IR drop of metal wire resistance. Multiply-accumulate (MAC) operation of 4-bit weight and width-modulated input can be performed in a single input step without additional logic operation. Furthermore, the effect of quantization training (QT) on the classification accuracy is investigated compared with post-training quantization (PTQ) with 4-bit weight. Lastly, a sufficiently low current variance of NAND cells obtained by the read-verify-write (RVW) scheme achieves satisfying accuracies of 98.14 and 89.6% for the MNIST and CIFAR10 images, respectively.