Showing papers on "Spice published in 2007"

Mosfet modeling for vlsi simulation: theory and practice

Abstract: Overview Review of Basic Semiconductor and pn Junction Theory MOS Transistor Structure and Operation MOS Capacitor Threshold Voltage MOSFET DC Model Dynamic Model Modeling Hot-Carrier Effects Data Acquisition and Model Parameter Measurements Model Parameter Extraction Using Optimization Method SPICE Diode and MOSFET Models and Their Parameters Statistical Modeling and Worst-Case Design Parameters

MOSFET modeling for IC design accurate for high frequencies

Abstract: The present invention presents methods for modeling the high frequency and noise characterization of MOSFETs. The models may be readily implemented as part of a SPICE or other simulation in a design flow. In particular, this invention is capable of providing a sub-circuit representation of a MOSFET that can accurately predicate a MOSFET's low frequency, high frequency, and noise characterizations. An interface is described through which a user may simultaneously optimize all of these characterizations. Further, methods are presented for building models that can predicate the variations in MOSFETs due to manufacturing processes and generate a corresponding corner model.

Waveform analysis and delay prediction for a CMOS gate driving RLC interconnect load

Abstract: This paper deals with the problem of estimating the performance of a CMOS gate driving RLC interconnect load. The widely accepted model for CMOS gate and interconnect line is used for the representation. The CMOS gate is modeled by an Alpha Power law model, whereas the distributed RLC interconnect is represented by an equivalent @p-model. The output waveform and the propagation delay of the inverter are analytically calculated and compared with SPICE simulations. The analytical driver-interconnect load model gives sufficiently close results to SPICE simulations for two different cases of slow and fast input ramps. For each case of stimulation, the model gives an insight to four regions of operation of the CMOS gate. The voltage waveform at the end of an interconnect line is obtained for each region of operation. The SPICE and analytical results for the output voltage waveform and propagation delay match very closely.

3-D Design and Analysis of Functional NEMS-gate MOSFETs and SETs

Abstract: Nanoelectromechanical system (NEMS)-gate metal- oxide-semiconductor field effect transistor (MOSFET) and single- electron transistor (SET) structures are investigated by combining 3-D design and SPICE simulation. First, the metal gate is simulated by using a 3-D simulator, which enables to design realistic 3-D device structures, and its movement is studied for different design parameters. It is demonstrated that a low stiffness design of the structure is essential for a low-voltage actuation. Results are compared with theoretical numerical simulation and a tunable capacitor model is then embedded in a SPICE simulator and coupled either with a transistor model for MOS-NEMS or with a newly developed SET analytical model for SET-NEMS. It is shown that the use of NEMS membrane can add new functionalities to conventional MOSFET and SET, such as very abrupt switching of the current, which can break theoretical limits of MOSFET, or modulation of Coulomb oscillations governing SET characteristics

Physics-Based PiN Diode SPICE Model for Power-Circuit Simulation

Abstract: A physics-based model for PiN power diodes is developed and implemented as a SPICE subcircuit. The model is based on a distributed equivalent circuit representation of the PiN base region, which is obtained by solving the ambipolar diffusion equation with the finite difference method. The model is validated against experimental characterization that is carried out on the commercial fast recovery power diodes. Comparisons between the results of the SPICE model with experimental and simulation results taken from the literature and from SILVACO mixed-mode simulations are also presented. Finally, the simulation of a realistic power circuit demonstrates the practical suitability of the proposed model for circuit design in terms of computational efficiency, convergence, and robustness.

Novel Hybrid Voltage Controlled Ring Oscillators Using Single Electron and MOS Transistors

Abstract: This paper proposes two kinds of novel hybrid voltage controlled ring oscillators (VCO) using a single electron transistor (SET) and metal-oxide-semiconductor (MOS) transistor. The novel SET/MOS hybrid VCO circuits possess the merits of both the SET circuit and the MOS circuit. The novel VCO circuits have several advantages: wide frequency tuning range, low power dissipation, and large load capability. We use the SPICE compact macro model to describe the SET and simulate the performances of the SET/MOS hybrid VCO circuits by HSPICE simulator. Simulation results demonstrate that the hybrid circuits can operate well as a VCO at room temperature. The oscillation frequency of the VCO circuits could be as high as 1 GHz, with a -71 dBc/Hz phase noise at 1 MHz offset frequency. The power dissipations are lower than 2 uW. We studied the effect of fabrication tolerance, background charge, and operating temperature on the performances of the circuits

Modeling Ion-Induced Pulses in Radiation-Hard SOI Integrated Circuits

Abstract: A common technique for hardening a circuit cell against single-event effects (SEE) is to use an RC delay or other time delay technique to slow down the response of a storage or memory cell. In order for this to work, we must have a good model for the duration of the output voltage pulse due to the ion strike on a given cell. Two-dimensional simulations determine the output voltage pulse shape due to an ion strike on a circuit cell within an integrated circuit. For SOI, the worst-case pulse occurs when the ion strike is near the center of the NMOS body (under the gate). It is very desirable to have a simple SPICE model for the SEE behavior because of the large number of circuit cells that need to be characterized. Two-dimensional (2D) simulations are translated into a ID format, from which closed-form physics-based equations are derived, which are then used in SPICE simulations. Test chips from a 0.15 mum SOI process are used to experimentally determine the LET threshold of six different circuits. The SPICE predictions of LET threshold are in good agreement with the experimental results. Because the SEE pulse widths in SOI circuits are much shorter than those in comparable bulk CMOS circuits, time-delay radiation hardening of SOI can be achieved with much less compromise of the speed of storage or memory cells.

Progress report of the single particle irradiation system to cell (SPICE)

Abstract: At the National Institute of Radiological Sciences (NIRS), we constructed a microbeam system in 2003, the single particle irradiation to cell, SPICE. From the beginning of 2005, we redesigned it to improve the stability of the optical alignment of the system, and obtained an reduction of the beam size proportional to the vertical dimension of the object slits. As a result, SPICE is now capable of producing a beam size of approximately 10 μm diameter, and the particle numbers controllable to an intensity as low as single particles per second, and therefore a single particle irradiation facility has been successfully implemented. Moreover, these conditions can be easily reproduced with a employing a routine procedure. We describe in detail the modifications of the beam line and results, demonstrating the improvements. In addition, results from our first biological experiments are shown.

A high-efficiency Class E inverter – computer model, laboratory measurements and SPICE simulation

Abstract: The paper presents the theoretical background, computer model, laboratory measurements and SPICE simulation results of a 323 W, 1 MHz Class E inverter operating with an efficiency of 97%. The inverter is built around a CoolMOS transistor from Infineon Technologies. The transistor belongs to a new generation of high quality, optimized for low conduction losses and high speed switching power MOSFET-s. The presented computer model of Class E inverter is based on a state-space description and allows computing the inverter parameters for the optimum operation. Its validity has been confirmed experimentally. The SPICE simulation of the inverter has been also carried out in order to obtain better agreement between measurement and calculation results.

DDCC based all-pass filters using minimum number of passive elements

Abstract: In this study, three first order all-pass filters are proposed using differential difference current conveyor (DDCC), a capacitor and a resistor without element-matching restriction. The theoretical results are verified with SPICE simulations.

Root-Mean-Square Measurement of Distinct Voltage Signals

Abstract: A circuit for measuring the root-mean-square (RMS) value of N distinct voltage signals, which employs two second-generation current conveyors and 2N + 1 metal-oxide-semiconductor transistors, is presented. The proposed circuit can find applications in measuring the RMS value of the output error signal of an artificial neural network (ANN). The presented network can also be used for realizing half-and full-wave rectifications. The proposed circuit does not use resistances and capacitances; therefore, it can operate at high frequencies. The results of the calculations are verified using SPICE simulations.

Designing SRCOs by combining SPICE and Verilog-A

Abstract: The design of single-resistance-controlled oscillators (SRCOs) is presented by using current followers (CF) and voltage followers (VF). First, the design of the followers is described by using SPICE and standard CMOS technology of 0.35 µm. Second, a SRCO is simulated in SPICE by using the designed CF and VF. Third, the SRCO is simulated in Verilog-A by using ideal and real behavioural models for the followers. Finally, the good agreement on the simulation results leads us to conclude on the usefulness to combine SPICE and Verilog-A to enhance analogue integrated circuit design.

A New Simulation Method for NBTI Analysis in SPICE Environment

Abstract: This paper presents a simulation framework for reliability analysis of circuits in the SPICE environment. The framework incorporates the degradation of physical parameters such as threshold voltage (Vtp) into circuit simulation and enables the design of highly reliable circuits. The parameter degradation is based on the numerical solution for the reaction-diffusion (R-D) mechanism, which is a general model applicable to various reliability effects such as NBTI, HCI, NCS, and SEE. In particular, the accuracy and efficiency of this method was verified for NBTI degradation with 130nm experimental and simulation data over a wide range of stress voltages and temperature. The model also accurately captures the dependence of NBTI on multiple diffusion species (H/H2), key process (Vth, tox) and environmental parameters (VDD, temperature). The circuit level performance of this method is verified with silicon data from ring-oscillator circuit. We also investigated the predicted impact of NBTI on representative digital circuits

Equivalent circuit models of quantum cascade lasers for SPICE simulation of steady state and dynamic responses

Abstract: The electrical equivalent circuits of quantum cascade lasers (QCLs) under steady state and under an ac small-signal are developed by employing simplified rate equations for electronic transitions between two levels and the rate equation for photon numbers. Two interactive circuits represent the steady state behaviour and another two coupled circuits model the ac small-signal performance of a QCL. The equivalent circuits are then used for SPICE simulation. The steady state equivalent circuit reproduces the light current curve of QCLs. The ac equivalent circuit yields the intensity modulation response, which matches almost exactly with the curve obtained from reported numerical calculations based on a third-order system model. In addition, the ac model is employed for SPICE simulation to give values of the modulation bandwidth for different values of photon lifetime. The SPICE model gives a slightly different curve for the bandwidth against photon lifetime from the curve plotted using the approximate analytical expression.

VHDL-AMS Modeling of Total Ionizing Dose Radiation Effects on CMOS Mixed Signal Circuits

Abstract: A hierarchical method for total dose effects simulation of large mixed signal circuits using VHDL-AMS is described. Simplified behavioral models (or macro-models) of small sub-circuits replace SPICE-level circuits. The behavioral models describe the electrical circuit behavior and its dependence on the radiation dose. The behavioral models of sub-circuits can be assembled into complex mixed signal circuits. As a result, the computational cost is reduced significantly compared to conventional SPICE-based methods. The VHDL-AMS method also allows bias-dependent total dose degradation to be coupled to the circuit and operational conditions. Simulation accuracy remains sufficient to determine critical performance metrics of the circuit as the circuit performance degrades with dose.

Bifurcation Behavior of SPICE Simulations of Switching Converters: A Systematic Analysis of Erroneous Results

Abstract: The SPICE simulation program is widely used as a brute force simulator for analyzing and designing switching power converters. Results from SPICE are mostly useful, but their integrity is sometimes questionable as erroneous results could be obtained which may not reflect the true behavior of the circuits being simulated. Various parameters in SPICE are crucial in controlling the convergence and accuracy of the simulated results, e.g., relative error tolerance and maximum integration step size. In this paper, we study the system consisting of the SPICE simulation algorithm and the circuit being simulated. Specifically, we describe the generation of flawed solutions in terms of bifurcation of the system under parameter variations. Erroneous results have been collected for different relative error tolerances, maximum integration step sizes, and parasitic inductance and capacitance. These flawed solutions can be analyzed in terms of the manifestation of period-doubling bifurcation and chaotic behavior under variation of selected simulation parameters. This paper provides a systematic approach to rationalizing the behavior of the SPICE simulator, its practical significance being in the identification of the ranges of simulation parameters for which flawed solutions can be produced.

An Efficient Technique for Leakage Current Estimation in Sub 65nm Scaled CMOS Circuits Based on Loading Effect

Abstract: With scaling of CMOS technologies, sub-threshold, gate and reverse biased junction band-to-band-tunneling leakage have increased dramatically. Together they account for more than 25% of power consumption in the current generation of leading edge designs. Different sources of leakage can affect each other by interacting through resultant intermediate node voltages. This is called the loading effect. In this paper, the authors propose a pattern dependent steady state leakage estimation technique that incorporates loading effect and accounts for all three major leakage components, namely the gate, band to band tunneling and sub-threshold leakage and accounts for transistor stack effect. The proposed estimation technique has been validated against SPICE and can be deployed on larger circuits where SPICE simulation is infeasible. In this paper, we report a speed up of 2,000-70,000times speed-up over SPICE simulation on smaller circuits, where spice simulation is feasible. Further results show that loading effect is a significant factor in leakage that worsens with technology scaling

A New Analog Buffer Using Low-Temperature Polysilicon Thin-Film Transistors for Active-Matrix Displays

Abstract: In this paper, a new source-follower-type analog buffer for active-matrix displays, designed by using low-temperature polysilicon thin-film transistors (TFTs), is proposed. The buffer, consisting of five n-type polysilicon TFTs, one bias voltage, and an additional control signal, exhibits high immunity to threshold voltage and mobility variations. The functionality of the proposed buffer was verified by HSPICE simulations. In order to obtain realistic simulations, the TFT model parameters used for the simulations were extracted from fabricated TFTs using the Silvaco tools (ATLAS). The proposed buffer has 7-bit output voltage with the dynamic output voltage range of 7.5 V ranging from 2.5 to 10 V and with resolution up to 0.03 V

Dynamic Model and Simulation for a 6/4 Switched Reluctance Machine System Assisted by Maxwell SPICE and Simplorer

Abstract: This paper presents a method for modeling and simulation of switched reluctance machine (SRM) system assisted by Maxwell SPICE tool and Simplorer environment. The nonlinear magnetization characteristics of flux linkage and torque for the machine have been considered and calculated by finite element analysis (FEA). From 2D FEA results, a dynamic equivalent circuit of SRM ECE model is constructed into Simplorer using Maxwell SPICE rules. The strategies of variation parameters speed PI control and the current chopped control (CCC) are used when SRM operates in the state of motoring due to SRM small signal model, whereas the variation parameters voltage PI control and angel position control (APC) are used in the state of generating. The simulation and experimental results for a 6/4 SRM system are presented and compared to demonstrate the validity of the modeling method.

A simple spice model for traveling wave semiconductor laser amplifier

Abstract: An equivalent lumped element electric circuit model for traveling wave semiconductor laser amplifier has been developed using the rate equation for carriers. SPICE simulation of the circuits gives results in close agreement with the experimental data and values from sophisticated analyses. The modulation bandwidth and transient response were examined by including parasitic elements in the intrinsic model. © 2007 Wiley Periodicals, Inc. Microwave Opt Technol Lett 49: 1558–1561, 2007; Published online in Wiley InterScience (www.interscience.wiley.com). DOI 10.1002/mop.22483

On estimating impact of loading effect on leakage current in sub-65nm scaled CMOS circuits based on Newton-Raphson method

Abstract: Different sources of leakage can affect each other by interacting through resulting intermediate node voltages. This is known as the loading effect, hi this paper, we propose a pattern dependent steady state leakage estimation technique that incorporates loading effect and addresses the three dominant sources of leakage, namely the sub-threshold, gate oxide and band-to-band tunneling leakages. We have developed a compact leakage model that supports iteration over node voltages based on Newton-Raphson method. The proposed estimation technique based on the compact model improves performance and capacity over SPICE. We report a speed up of 18,000X over SPICE. Results show that loading effect is a significant factor in leakage and worsens with technology scaling.

A design methodology for low-power MCML ring oscillators

Abstract: In this paper, a low-power design method for MCML based ring oscillators is presented. The proposed method takes into account the parasitic capacitances of the MOS transistors. To validate it, some ring oscillators with different oscillation frequencies were designed in a 0.18 mum CMOS technology. SPICE simulations demonstrate the effectiveness of the design method.

SPICE-Compatible Cavity and Transmission Line Model for Power Bus with Narrow Slots

Abstract: Segmental lumped circuits are derived from coupled transmission line model for a narrow slot on the power bus. Both electric and magnetic coupling are taken into account by distributed inductances and capacitances. Then a SPICE- compatible circuit model for the power bus with the narrow slot is proposed. In this model, the segmental lumped circuits are connected to the equivalent circuit, which is derived by a hybrid cavity model and segmentation method for irregular power/ground planes. The model is validated by comparing with the calculations of finite element method (FEM) for the self or mutual impedances of the two port networks located in the power bus.

Coupling Analysis of PCB-Chassis Systems with Signal Lines and Via Structures using SPICE

Abstract: This paper describes the SPICE modeling of printed circuit boards (PCBs) with signal lines and via structures electrically connected to a metal chassis First, a PCB model is proposed considering the coupling between signal lines and the power bus due to via structures Next, the model is expanded to include the chassis and grounding posts The calculated results using SPICE are shown to be consistent with experimental data Furthermore, positioning of the grounding posts near the edges of the PCB is shown experimentally and numerically to reduce radiated emissions

Protection Functions in Integrated Low Side Switches

Abstract: This paper presents the over current and over temperature protective functions integrated in a low side switch. The design is focused on evaluating and controlling the over current and over temperature thresholds value spreads, to assure the needed accuracy. A simple analytical model is developed for predicting the threshold spreads. SPICE simulation, including Monte Carlo analysis, is used to get a better estimation for the two thresholds variation.