Showing papers on "Strained silicon published in 1991"

Porous silicon formation: A quantum wire effect

Abstract: Porous silicon layers grown on nondegenerated p‐type silicon electrodes in hydrofluoric acid electrolytes are translucent for visible light, which is equivalent to an increased band gap compared to bulk silicon. It will be shown that a two‐dimensional quantum confinement (quantum wire) in the very narrow walls between the pores not only explains the change in band‐gap energy but may also be the key to better understanding the dissolution mechanism that leads to porous silicon formation.

Silicon-on-Insulator Technology: Materials to VLSI

Abstract: 1 Introduction.- 2 SOI Materials.- 2.1 Introduction.- 2.2 Heteroepitaxial techniques.- 2.2.1 Silicon-on-Sapphire (SOS).- 2.2.2 Other heteroepitaxial SOI materials.- 2.2.2.1 Silicon-on-Zirconia (SOZ).- 2.2.2.2 Silicon-on-Spinel.- 2.2.2.3 Silicon on Calcium Fluoride.- 2.3 Dielectric Isolation (DI).- 2.4 Polysilicon melting and recrystallization.- 2.4.1 Laser recrystallization.- 2.4.2 E-beam recrystallization.- 2.4.3 Zone-melting recrystallization.- 2.5 Homoepitaxial techniques.- 2.5.1 Epitaxial lateral overgrowth.- 2.5.2 Lateral solid-phase epitaxy.- 2.6 FIPOS.- 2.7 Ion beam synthesis of a buried insulator.- 2.7.1 Separation by implanted oxygen (SIMOX).- 2.7.1.1 "Standard"SIMOX.- 2.7.1.2 Low-dose SIMOX.- 2.7.1.3 ITOX.- 2.7.1.4 SMOXMLD.- 2.7.1.5 Related techniques.- 2.7.1.6 Material quality.- 2.7.2 Separation by implanted nitrogen (SIMNI).- 2.7.3 Separation by implanted oxygen and nitrogen (SIMON).- 2.7.4 Separation by implanted Carbon.- 2.8 Wafer Bonding and Etch Back (BESOI).- 2.8.1 Hydrophilic wafer bonding.- 2.8.2 Etch back.- 2.9 Layer transfer techniques.- 2.9.1 Smart-Cut(R).- 2.9.1.1 Hydrogen / rare gas implantation.- 2.9.1.2 Bonding to a stiffener.- 2.9.1.3 Annealing.- 2.9.1.4 Splitting.- 2.9.1.5 Further developments.- 2.9.2 Eltran(R).- 2.9.2.1 Porous silicon formation.- 2.9.2.2 The original Eltran(R) process.- 2.9.2.3 Second-generation Eltran(R) process.- 2.9.3 Transferred layer material quality.- 2.10 Strained silicon on insulator (SSOI).- 2.11 Silicon on diamond.- 2.12 Silicon-on-nothing (SON).- 3 SOI Materials Characterization.- 3.1 Introduction.- 3.2 Film thickness measurement.- 3.2.1 Spectroscopic reflectometry.- 3.2.2 Spectroscopic ellipsometry.- 3.2.3 Electrical thickness measurement.- 3.3 Crystal quality.- 3.3.1 Crystal orientation.- 3.3.2 Degree of crystallinity.- 3.3.3 Defects in the silicon film.- 3.3.3.1 Most common defects.- 3.3.3.2 Chemical decoration of defects.- 3.3.3.3 Detection of defects by light scattering.- 3.3.3.4 Other defect assessment techniques.- 3.3.3.5 Stress in the silicon film.- 3.3.4 Defects in the buried oxide.- 3.3.5 Bond quality and bonding energy.- 3.4 Carrier lifetime.- 3.4.1 Surface Photovoltage.- 3.4.2 Photoluminescence.- 3.4.3 Measurements on MOS transistors.- 3.4.3.1 Accumulation-mode transistor.- 3.4.3.2 Inversion-mode transistor.- 3.4.3.3 Bipolar effect.- 3.5 Silicon/Insulator interfaces.- 3.5.1 Capacitance measurements.- 3.5.2 Charge pumping.- 3.5.3 ?-MOSFET.- 4 SOI CMOS Technology.- 4.1 SOI CMOS processing.- 4.1.1 Fabrication yield and fabrication cost.- 4.2 Field isolation.- 4.2.1 LOCOS.- 4.2.2 Mesa isolation.- 4.2.3 Shallow trench isolation.- 4.2.4 Narrow-channel effects.- 4.3 Channel doping profile.- 4.4 Source and drain engineering.- 4.4.1 Silicide source and drain.- 4.4.2 Elevated source and drain.- 4.4.3 Tungsten clad.- 4.4.4 Schottky source and drain.- 4.5 Gate stack.- 4.5.1 Gate material.- 4.5.2 Gate dielectric.- 4.5.3 Gate etch.- 4.6 SOI MOSFET layout.- 4.6.1 Body contact.- 4.7 SOI-bulk CMOS design comparison.- 4.8 ESD protection.- 5 The SOI MOSFET.- 5.1 Capacitances.- 5.1.1 Source and drain capacitance.- 5.1.2 Gate capacitance.- 5.2 Fully and partially depleted devices.- 5.3 Threshold voltage.- 5.3.1 Body effect.- 5.3.2 Short-channel effects.- 5.4 Current-voltage characteristics.- 5.4.1 Lim & Fossum model.- 5.4.2 C?-continuous model.- 5.5 Transconductance.- 5.5.1 gm/ID ratio.- 5.5.2 Mobility.- 5.6 Basic parameter extraction.- 5.6.1 Threshold voltage and mobility.- 5.6.2 Source and drain resistance.- 5.7 Subthreshold slope.- 5.8 Ultra-thin SOI MOSFETs.- 5.8.1 Threshold voltage.- 5.8.2 Mobility.- 5.9 Impact ionization and high-field effects.- 5.9.1 Kink effect.- 5.9.2 Hot-carrier degradation.- 5.10 Floating-body and parasitic BJT effects.- 5.10.1 Anomalous subthreshold slope.- 5.10.2 Reduced drain breakdown voltage.- 5.10.3 Other floating-body effects.- 5.11 Self heating.- 5.12 Accumulation-mode MOSFET.- 5.12.1 I-V characteristics.- 5.12.2 Subthreshold slope.- 5.13 Unified body-effect representation.- 5.14 RF MOSFETs.- 5.15 CAD models for SOI MOSFETs.- 6 Other SOI Devices.- 6.1 Multiple-gate SOI MOSFETs.- 6.1.1 Multiple-gate SOI MOSFET structures.- 6.1.1.1 Double-gate SOI MOSFETs.- 6.1.1.2 Triple-gate SOI MOSFETs.- 6.1.1.3 Surrounding-gate SOI MOSFETs.- 6.1.1.4 Triple-plus gate SOI MOSFETs..- 6.1.2 Device characteristics.- 6.1.2.1 Current drive.- 6.1.2.2 Short-channel effects.- 6.1.2.3 Threshold voltage.- 6.1.2.4 Volume inversion.- 6.1.2.5 Mobility.- 6.2 MTCMOS/DTMOS.- 6.3 High-voltage devices.- 6.3.1 VDMOS and LDMOS.- 6.3.2 Other high-voltage devices.- 6.4 Junction Field-Effect Transistor.- 6.5 Lubistor.- 6.6 Bipolar junction transistors.- 6.7 Photodiodes.- 6.8 G4 FET.- 6.9 Quantum-effect devices.- 7 The SOI MOSFET in a Harsh Environment.- 7.1 Ionizing radiations.- 7.1.1 Single-event phenomena.- 7.1.2 Total dose effects.- 7.1.3 Dose-rate effects.- 7.2 High-temperature operation.- 7.2.1 Leakage current.- 7.2.2 Threshold voltage.- 7.2.3 Output conductance.- 7.2.4 Subthreshold slope.- 8 SOI Circuits.- 8.1 Introduction.- 8.2 Mainstream CMOS applications.- 8.2.1 Digital circuits.- 8.2.2 Low-voltage, low-power digital circuits.- 8.2.3 Memory circuits.- 8.2.3.1 Non volatile memory devices.- 8.2.3.2 Capacitorless DRAM.- 8.2.4 Analog circuits.- 8.2.5 Mixed-mode circuits.- 8.3 Niche applications.- 8.3.1 High-temperature circuits.- 8.3.2 Radiation-hardened circuits.- 8.3.3 Smart-power circuits.- 8.4 Three-dimensional integration.

Stress‐related problems in silicon technology

Abstract: The silicon integrated‐circuits chip is built by contiguously embedding, butting, and overlaying structural elements of a large variety of materials of different elastic and thermal properties. Stress develops in the thermal cycling of the chip. Furthermore, many structural elements such as CVD (chemical vapor deposition) silicon nitride, silicon dioxide, polycrystalline silicon, etc., by virtue of their formation processes, exhibit intrinsic stresses. Large localized stresses are induced in the silicon substrate near the edges and corners of such structural elements. Oxidation of nonplanar silicon surfaces produces another kind of stress that can be very damaging, especially at low oxidation temperatures. Mismatch of atomic sizes between dopants and the silicon, and heteroepitaxy produce another class of strain that can lead to the formation of misfit dislocations. Here we review the achievements to date in understanding and modeling these diverse stress problems.

Semiconductor device having a passivation layer with silicon nitride layers

Abstract: A semiconductor device is protected by a passivation layer, which includes underlying and overlying silicon nitride layers deposited by the plasma-assisted CVD method by changing layer forming conditions. The silicon nitride layers respectively have their intrinsic compressive stresses. The underlying silicon nitride layer in contact with a metal wiring layer has the intrinsic compressive stress of 3×10 9 to 1×10 10 dyne/cm 2 . The overlying silicon nitride layer has the intrinsic compressive stress which is less than or equal to half of the intrinsic compressive stress of the underlying silicon nitride layer. The underlying and overlying silicon nitride layers have different degrees of the hydrogen content. The underlying silicon nitride layer has the hydrogen content of 0.5×10 20 to 5×10 21 atm/cm 3 . The overlying silicon nitride layer has the hydrogen content which is more than or equal to twice of the hydrogen content of the underlying silicon nitride layer.

Breakdown voltage enhancement for devices on thin silicon layer/silicon dioxide film

Abstract: Studies of high-voltage lateral device structures on a thin silicon layer over silicon dioxide have been carried out. It was found both theoretically and experimentally that over 600-V devices can be realized using a structure consisting of an n diffusion layer over a 15- mu m-thick high-resistivity n/sup -/ silicon layer over 3- mu m silicon dioxide (SOI). A method is presented to enhance breakdown voltage by applying a large share of the voltage to the bottom oxide. >

Process for creating fully-recessed field isolation regions by oxidizing a selectively-grown epitaxial silicon layer

Abstract: A low-stress process for creating field isolation regions on a silicon substrate that are fully recessed with respect to active areas. The field isolation regions, which have no bird's beak transition regions at their edges, are created by oxidizing an epitaxially-grown layer of silicon, the edges of which are isolated from active area silicon by a an oxide-backed silicon nitride spacer. Each nitride spacer is contiguous with a horizontal silicon nitride layer segment that protects an active area from oxidation during thermal field oxidation. A modification of the process, which requires the deposition of an additional silicon dioxide layer and a wet etch to remove spacers created from that additional layer, further reduces stress during thermal oxidation of the epitaxially-grown silicon layer by providing a void around the periphery of the epitaxial layer for expansion during the thermal oxidation thereof.

Nonvolatile semiconductor device

Abstract: In a nonvolatile semiconductor memory device with a two-layer gate structure, an interlayer insulating film is formed on a floating gate electrode of, e.g., polycrystalline silicon. The interlayer insulating film has a four-layer structure in which a first silicon nitride film, a first silicon oxide film, a second silicon nitride film and a second silicon oxide film are laminated in this order on the floating gate electrode, or a two-layer structure in which a first silicon nitride film and a first silicon oxide film are laminated in this order on the floating gate electrode. With the above structure, the threshold voltage of the semiconductor device is stabilized even after data-erase operation. Since, moreover, the first silicon oxide film can be formed by oxidizing the first silicon nitride film, then the quality of the first silicon oxide film can be enhanced, and accordingly the charge retaining properties of the device can be increased.

Thermal inkjet printhead structure and method for making the same

Abstract: An improved thermal inkjet printhead having MOSFET drive transistors incorporated therein. The gate of each MOSFET transistor is formed by applying a layer of silicon dioxide onto a silicon substrate, applying a layer of silicon nitride onto the silicon dioxide, and applying a layer of polycrystalline silicon onto the silicon nitride. Portions of the substrate surrounding the gate are oxidized, forming field oxide regions. Drain and source regions are then conventionally formed, followed by the application of a protective dielectric layer onto the field oxide, drain, source, and gate. A resistive layer is deposited on the dielectric layer and directly connected to the source, drain, and gate. A conductive layer is deposited on a portion of the resistive layer, ultimately forming both covered and uncovered regions thereof. The uncovered region functions as a heating resistor, and the covered regions function as electrical contacts to the transistor and resistor.

Method for forming thin silicon membrane or beam

Abstract: A method is disclosed for forming thin, suspended membranes of epitaxial silicon material. Silicon oxide strips (12) having a predetermined thickness are first formed on a silicon substrate (10). A gap (14) provided between adjacent pairs of strips (12) is preferably less than or equal to about 1.4 times the thickness of the silicon oxide strips (12). The underlying silicon substrate (10) is exposed within these gaps (14) in the silicon oxide layer, whereby the gaps (14) provide seed holes for subsequent epitaxial growth from the silicon substrate (10). Epitaxial silicon is grown through the gaps (14) and then allowed to grow laterally over the silicon oxide strips (12) to form a continuous layer (20) of epitaxial silicon over the silicon oxide strips (12). The backside of the silicon substrate (10), i.e., the surface opposite the surface having the silicon oxide strips (12), is then masked to delineate the desired diaphragm and microbridge pattern. The silicon is etched conventionally from the backside of the silicon substrate (10). Etching is terminated substantially automatically by the presence of the silicon oxide strips (12). The thin, single crystal silicon membranes thus formed are suitable for use as diaphragms and microbridges in a microaccelerometers or a pressure sensor.

Silicon carbide light emitting diode and a method for the same

Abstract: There are provided silicon carbide light emitting diodes having a p-n junction which is constituted by a p-type silicon carbide single-crystal layer and an n-type silicon carbide single-crystal layer formed thereon. In cases where light emission caused by recombination of free excitons is substantially utilized, at least a part of the n-type silicon carbide layer adjacent to the interface of the p-n junction is doped with a donor impurity at a concentration of 5×1016 cm-3 or lower. In cases where light emission caused by acceptor-associated recombination is substantially utilized, the p-type silicon carbide layer is doped with an acceptor impurity and at least a part of the n-type silicon carbide layer adjacent to the interface of the p-n junction is doped with a donor impurity at a concentration of 1×1018 cm-3 or higher. Also provided are a method for producing such silicon carbide light emitting diodes and a method for producting another silicon carbide light emitting diode.

Process for making strain-compensated bonded silicon-on-insulator material free of dislocations

Abstract: A silicon-on-insulator material is formed by a method which includes the steps of forming a p-type silicon epitaxial layer, doped with boron and a higher concentration of germanium, on the surface of a semiconductor silicon substrate, forming an additional silicon epitaxial layer on the p-type silicon epitaxial layer, forming an oxide layer on the additional silicon epitaxial layer, forming an oxide layer on another semiconductor silicon substrate, forming a laminate by bringing into contact, at room temperature, the oxide layers thereby bonding together the substrates, etching the silicon substrate provided with the silicon epitaxial layers, with an isotropic etch to remove most of this silicon substrate, exposing the laminate to an anisotropic etch for this silicon substrate until the remainder of this silicon substrate is removed but only a part of the p-type epitaxial layer is removed and then exposing the resultant structure to an additional isotropic etch for the p-type epitaxial layer for a time sufficient only to remove only the remainder of the p-type epitaxial layer.

Process for producing an arsenic-doped smooth polycrystalline silicon layer for very large scale integrated circuits

Abstract: In a multistage process for producing a smooth polycrystalline silicon layer, in particular a layer with low arsenic doping, for very large scale integrated circuits, by thermal decomposition of gaseous compounds containing the elements, a doped layer and an undoped silicon layer above the doped layer are deposited directly one after the other in a two-stage process. Initially, a surface-covering arsenic layer being at most a few atoms thick, is deposited as a preliminary lining. Then an undoped amorphous silicon layer is deposited on the arsenic layer at a temperature of less than 580° C. Subsequently, the silicon layer is uniformly doped with the arsenic layer serving as a diffusion source, by temperature treatment. Simultaneously, the amorphous silicon is made into a polycrystalline silicon layer.

A defect-pool model for near-interface states in amorphous silicon thin-film transistors

Abstract: We present evidence that the majority of deep states located near to the gate-insulator interface in amorphous silicon (a-Si) thin-film transistors are part of a defect pool of silicon dangling-bond states, whose density and energy position within the energy gap of the a-Si are determined by the Fermi energy during thermal equilibration. Transistors made with silicon nitride and silicon oxide gate insulators tend to have different densities-of-states distributions. We show it is possible to modify the entire energy distribution of states, by annealing the transistors with an applied gate bias. The density of states and their energy distribution re-equilibrates to the new Fermi energy position, causing the density of states to be increased or decreased in different parts of the bandgap. In particular, an oxide transistor can be made to have a density-of-states distribution similar to a nitride transistor by suitable positive-bias annealing, and a nitride transistor can be made to have a density-of...

Semiconductor device with nitrided gate insulating film

Abstract: A semiconductor device formed on a silicon substrate consisting of the steps of producing a silicon oxide film on the silicon substrate, producing a thin silicon nitride film on the silicon oxide film, thermally nitriding the silicon nitride film in an atmosphere of nitrogenous gas, producing a conductive film on the silicon nitride film nitrided in the atmosphere of the nitrogenous gas, producing a gate region from the silicon oxide film, the silicon nitride film, and the conductive film, a channel region being positioned under the gate region in the silicon substrate, producing a source region in the silicon substrate adjacent to one side of the channel region, producing a drain region in the silicon substrate adjacent to another side of the channel region, and producing wiring regions on the source region, the drain region, and the gate region.

Semiconductor device of band-to-band tunneling type

Abstract: A semiconductor device of band-to-band tunneling type including a silicon substrate, a first gate electrode formed by a highly doped surface region of the silicon substrate, a first silicon oxide film formed on a surface of the surface region, a silicon thin film formed on the first silicon oxide film, a second silicon oxide film formed on a surface of the thin silicon film, and a second gate electrode formed by a metal film applied on a surface of the second silicon oxide film. In the thin silicon film, there are formed P and N type regions side by side to constitute a PN junction. When a gate bias voltage is applied across the first and second gate electrodes, a band bend having a large height and inclination in a direction perpendicular to the thin silicon film is produced in the depletion region in the vicinity of the PN junction. Minority carriers brought up from the valence band into the conduction band by tunneling due to the band bend are conducted through the PN junction under the influence of a reverse bias voltage applied across the PN junction. The band bend can be made large at will by increasing the gate bias voltage, so that it is possible to obtain a large tunneling current.

Application of electronic properties of germanium to inhibit n-type or p-type diffusion in silicon

Abstract: A method of inhibiting dopant diffusion in silicon using germanium is provided. Germanium is distributed in substitutional sites in a silicon lattice to form two regions of germanium interposed between a region where dopant is to be introduced and a region from which dopant is to be excluded, the two germanium regions acting as a dopant diffusion barrier.

Semiconductor device having silicon carbide grown layer on insulating layer and MOS device

Abstract: A semiconductor device is manufactured by forming an epitaxial layer (22) insulated from a silicon substrate (2), and forming a device in the epitaxial layer (22). On the semiconductor substrate (2), a silicon dioxide layer (4) is formed (FIG. 2A). Then the silicon dioxide layer (4) is provided with openings (14) (FIG. 2D). Silicon carbide is grown until it protrudes from the openings (14) to thereby form a silicon carbide seed crystal layer (16) (FIG. 2E). Next, oxidation is carried out, allowing a field oxide layer (20) to be connected at the portion under the openings (14) and the silicon carbide seed crystal layer (16) to be insulated from the silicon substrate (2). Thereafter, epitaxial growth is effected from the silicon carbide seed crystal layer (16). The growth is stopped before silicon carbide grown layers (22) connect to one another, thus obtaining epitaxially grown layers (22) having regions which are separate from one another. The MOS device is formed in this epitaxially grown layer (22). The silicon carbide grown layer (22) is isolated from the silicon substrate (2) and formed as regions isolated from one another, having a uniform plane bearing. Accordingly, the layer (22) causes no electrostatic capacitance due to the absence of a pn junction with the silicon substrate (2) or with an adjacent layer (22), allowing high-speed operation of the device. Moreover, the unique plane bearing facilitates control during the manufacturing process.

Method of making a through hole in multi-layer insulating films

Abstract: A semiconductor device with an electrode wiring structure comprises at least one diffused region provided in a semiconductor substrate, a silicon oxide layer covering the substrate surface, a silicon nitride layer provided on the silicon oxide layer, a through-hole reaching the diffused region through the silicon oxide layer from an upper surface of the silicon nitride layer, a silicon semiconductor layer filled in the through-hole and serving as an electrode wiring layer, and an interconnection layer electrically connected to the diffused region through the silicon semiconductor layer. According to the structure, since the silicon oxide layer is covered with the silicon nitride layer, unwanted contaminations such as phosphorus, boron, etc., previously contained in the silicon oxide layer are not added to the silicon semiconductor layer during its growth process. Therefore, the electrode wiring layer of silicon semiconductor having controlled conductivity can be provided.

Schottky barrier gate type field effect transistor

Abstract: The semiconductor device somprises a silicon substrate, a boron-doped high resistant silicon carbide layer formed on said silicon substrate and a silicon carbide layer formed on said high resistant silicon carbide layer.

Filling contact hole with selectively deposited EPI and poly silicon

Abstract: A semiconductor device includes a semiconductor layer, an insulating layer on the semiconductor layer, including a discontinuity therein, a monocrystalline silicon layer on a portion of semiconductor layer defined by the discontinuity, a non-monocrystalline silicon layer on the monocrystalline silicon layer, and a wiring layer on the non-monocrystalline silicon layer

Method for fabricating silicon-on-insulator structures

Abstract: A fabrication method for forming SOI structures where perfect material is grown epitaxially on a substrate and then, through a series of selective etches and oxidations, an insulating layer is formed below the epitaxial silicon. In the method, low temperature epitaxial techniques are employed to grow a layered structure including a first layer p++ silicon on a substrate wafer, a layer of intrinsic silicon is then formed on the first p++ silicon layer, and a second layer of p++ silicon is formed on the intrinsic silicon layer, and a finally a layer of p-silicon is fabricated on top of the second p++ silicon layer. Grooves are formed through the p-layer, the second p++ silicon layer, the intrinsic silicon layer, and stopped in the first p++ silicon layer. An etch is then employed to remove the intrinsic layer long enough for the p++ silicon layer to be totally undercut, leaving an air gap between the two p++ silicon layers. An oxidation step is then performed to form a bottom insulator consisting of the oxidized first p++ silicon layer and on an upper insulator consisting of the oxidized second p++ silicon layer.

Method for forming a semiconductor device isolation region

Abstract: A method for forming a semiconductor device isolation region including steps of forming a first silicon oxide film on a silicon substrate, depositing a first silicon nitride film over the first silicon oxide film, and removing the first silicon oxide film and first silicon nitride film in a device isolation region by using a resist pattern, which is formed by a one-time photolithographic step, as a mask so as to expose the surface of the silicon substrate, removing the resist pattern, and oxidizing the exposed surface of the silicon substrate so as to form a second silicon oxide film having a smaller thickness than the first silicon oxide film and to deposit a second silicon nitride film, removing the second silicon nitride film by anisotropic etching until the second silicon oxide film is exposed in the device isolation region so as to make the second silicon nitride film remain as the side wall portion of the silicon nitride film in only the opening side wall portion of the first silicon nitride film, etching the second silicon oxide film in the opening of the first silicon nitride film on a self-aligning basis by using as etching masks the first silicon nitride film and the side wall portion of the second silicon nitride film remaining on the opening side wall portion of the first silicon nitride film, and selectively carrying out oxidation so as to form a thick silicon oxide film in the device isolation region.

Zone melted recrystallized silicon on diamond

Abstract: In silicon-on-diamond (SOD) technology, diamond replaces the silicon-dioxide in the silicon-on-insulator structure. Diamond is good thermal conductor unlike silicon dioxide and a good electrical insulator like silicon dioxide. A high grade, high purity device-quality silicon wafer is chosen. An insulating diamond film of about 0.5 um or any suitable thickness is grown on the whole silicon wafer, including the rim area. A polycrystalline silicon of about 2 microns thick or so is then deposited on the whole wafer, including the rim area. Using the rim area silicon as the seed the polycrystalline silicon crystallizes into a single crystal by a zone melting recrystallization technique. The rim area is scribed off the wafer, leaving a recrystallized silicon-on-diamond (FIG. 1d). The structure top to bottom is recrystallized silicon-diamond and silicon-substrate. The structure is similar to ZMR SOI, but the insulator here is diamond instead of silicon dioxide and is therefore called ZMR SOD. The devices, such as MOSFETS, Bipolar transistors, JFETS and diodes, are fabricated in the recrystallized silicon that sits on top of the diamond film.

Microporous crystalline silicon of increased band-gap for semiconductor applications

Abstract: A process is disclosed for producing microporous crystalline silicon which has a band-gap substantially increased relative to that of normal crystalline silicon. This process involves the preparation of quantum wires of silicon by means of a chemical attack method carried out on silicon that has been doped such that it conducts electricity substantially via the effective transport of electric charge by means of so-called holes. The microporous crystalline silicon thus produced is in the form of a discrete mass having a bulk-like, interconnected crystalline silicon structure of quantum wires whose band-gap is greater than normal crystalline silicon. Because of this increased band-gap this microporous crystalline silicon may be used as an active element in applications such as tandem solar cells.

Method of manufacturing minimum counterdoping in twin well process

Abstract: An improved method for manufacturing high density CMOS integrated circuits which minimizes counterdoping of the N and P well structures includes providing a composite masking layer which has layers of silicon oxide, polycrystalline silicon and silicon nitride over a silicon monocrystalline substrate. A mask layer pattern is formed from the composite masking layer by lithography and anisotropic etching which removes the silicon nitride and the portion of the thickness of the polycrystalline silicon over areas designated to be the N well structure. The mask layer pattern is subjected to isotropic etching of the polycrystalline silicon to remove the remaining exposed thickness of polycrystalline silicon and to undercut etch the polycrystalline silicon under the silicon nitride portion of the mask layer pattern. The N well structure is ion implanted and formed by using the silicon nitride layer portion of the mask layer pattern as the mask. The silicon substrate over the N well and the exposed the polycrystalline silicon layer under the silicon nitride layer of the mask layer pattern is oxidized to form an N well silicon oxide pattern. The mask layer pattern is removed. The P well structure is ion implanted and formed using the N well silicon oxided pattern as the mask. The P well structure has minimized counterdoping by these process steps. All the silicon oxide from the surface of the silicon substrates are removed. Field oxide isolating structures are formed at the juncture of P well and N well structures.

Optically activated silicon microresonator transducers: An assessment of material properties

Abstract: During the fabrication of silicon microresonators, boron is diffused into areas of the silicon wafer to define a beam structure. The subsequent chemical etching of the silicon is inhibited in these highly doped regions. However, since the boron atom is smaller than the silicon atom, the impurity diffusion causes a lattice contraction and hence a tensile stress in the beam. This tension modifies the resonance frequency, and by monitoring this change we can quantify the strain to which the resonator is subjected. The Young's modulus of boron-doped silicon is also determined and shown to be slightly smaller than the bulk semiconductor value. Additionally the stiffness of thin aluminium films deposited upon the silicon beams is found to be substantially smaller than that of the bulk metal. The frequency response of these layered microresonators to temperature and optical irradiance variations is also assessed, providing further insight into the thermal, mechanical and optical properties of these thin-film materials.

Silicon film with improved thickness control

Abstract: A method of fabricating a silicon film with improved thickness control and low defect density. The method comprises implanting a silicon wafer (19) with hydrogen ions to produce a layer of n-type silicon (18) having a precisely controlled thickness. Bonding the n-type silicon layer (18) to an oxidized surface (17) of a handle wafer (21) while using a temperature of 200 degrees Celsius. Etching the silicon wafer (19) to the boundary of the n-type layer (18). Annealing the silicon to drive out the hydrogen ions, leaving a silicon film (18) with a precisely controlled thickness and of the same type as the original silicon wafer (19).

Deposition of germanium thin films on silicon dioxide employing interposed polysilicon layer

Abstract: The invention is a method of depositing a layer of polycrystalline silicon on a silicon dioxide substrate until the layer of polycrystalline silicon is thick enough to support the deposition of germanium thereon, but while thin enough to substantially avoid the deleterious effects on the characteristics of semiconductor device structure that the deposition of polycrystalline silicon would otherwise potentially cause. The polycrystalline layer is then exposed to a germanium containing gas at a temperature below the temperature at which germanium will deposit on silicon dioxide alone while preventing native growth of silicon dioxide on the polycrystalline silicon layer, and for a time sufficient for a desired thickness of polycrystalline germanium to be deposited on the layer of polycrystalline silicon.

Transient Temperature Profiles in Silicon Films during Pulsed Laser Annealing

Abstract: Transient temperature profiles have been studied theoretically in silicon film heated by a single shot of a laser light pulse for several substrate structures. The molten silicon region is very shallow and disappears completely within a few tens of ns in (poly)crystalline silicon. It exists for more than a few hundred ns in amorphous silicon and also in silicon films on an oxide substrate. In silicon/oxide/conductive-substrate structures, the sustaining time of the molten silicon region is shortened by thinning the oxide film. Numerical results are compared with approximate relations derived from a simple physical picture.

A field emission device employing a layer of single-crystal silicon

Abstract: A variety of field emission devices (308) and field emission device structures which employ non-substrate layers of single-crystal silicon (203) are provided. By employing non-substrate layers of single-crystal silicon (203), improved emission control is achieved and improved performance controlling devices (406) can be formed within the device structure.