Showing papers on "Switched capacitor published in 1981"

A low-noise chopper-stabilized differential switched-capacitor filtering technique

Abstract: Describes the implementation of a wide dynamic range voiceband switched-capacitor filter using a differential chopper-stabilized configuration. The noise behavior of switched-capacitor filters is discussed qualitatively, and the effects of the chopper stabilization on the noise performance is analyzed. Experimental results from a fifth-order low-pass voiceband prototype are presented.

Effects of the op amp finite gain and bandwidth on the performance of switched-capacitor filters

Abstract: A pair of complementary strays-insensitive switched-capacitor (SC) integrator circuits are analyzed to determine the errors in their transfer functions due to the finite gain and finite bandwidth of the op amp. The results are used to predict the transfer function deviation of biquadratic filter sections and LC ladder simulations. It is shown that while the effect of finite op amp gain is similar to that encountered in active-RC filters, SC filters are much more tolerant of the finite op amp bandwidth. However, the relationship between transfer function error and finite op amp bandwidth is an exponential one as contrasted to the linear relationship of active-R C filters. Experimental results are presented.

Switched-capacitor building blocks for adaptive systems

Abstract: A number of switched-capacitor (SC) building blocks useful in adaptive systems are presented. These include a phase-lock loop, a tracking filter, a second-order equalizer with programmable gain, zeros' frequency and zeros' Q factor, a quadrature sine-wave generator, and a synchronous demodulator. It is shown, how a number of these signal processing blocks can be combined together to produce an adaptive channel equalizer. The operation of most of the circuits presented has been verified using discrete prototypes.

Switched capacitor n-path filter

Abstract: A switched capacitor N-path filter in which all capacitors that introduce delay in the paths, in that they have memory and are characterized such that the new charge flow into each such capacitor during each commutation cycle depends on the old charge on it from the previous commutation cycle, are replaced with an associated plurality of N-commutating capacitors.

FSK Demodulator employing a switched capacitor filter and period counters

Abstract: An FSK demodulation circuit especially suited for integrated construction is provided. The demodulating circuit uses N counters and a counter selector circuit for sequentially switching the counters at every zero-cross point in the received FSK signal. Sensitivity of demodulation is improved by N-time zero-cross detection rather than counting the time between two adjacent zero-cross points. The FSK demodulation circuit uses a Switched Capacitor Bandpass Filter whose characteristics are changed by changing the frequency of an internal clock using simple dividing circuitry.

Switched capacitor filter utilizing a differential input and output circuit and method

Abstract: An integrated circuit employing a differential amplifier and switched capacitor networks to provide filtering techniques. The differential amplifier utilizes a feedback circuit between its inputs and outputs. A switched capacitor network coupled to the inputs of the amplifier and a second switched capacitor network coupled to the outputs of the amplifier provide the requisite filtering necessary for analog-to-digital encoding or digital-to-analog decoding. The differential configuration allows for less noise and better power supply rejection, whereby allowing for a higher signal-to-noise ratio.

Monolithic programmable gain-integrator stage

Abstract: A switched capacitor gain stage (110, 120) having a programmable gain factor. This gain factor is determined by the connection of desired gain determining components (14-17; 25-28) contained within a component array (100, 101). A sample and hold circuit (46) is provided for the storage of the error voltage of the entire gain-integrator stage. This stored error voltage (Verror) is inverted and integrated one time for each integration of the input voltage (Vin), thus eliminating the effects of the inherent offset voltages of the circuit from the output voltage (Vout).

Bilinear switched-capacitor ladder filters

Abstract: Design techniques are described for parasitic-insensitive switched-capacitor ladder filters, whose response is related to that of continuous-time filters by the bilinear s-to-z transformation. A modification of the process, which reduces the necessary number of amplifiers but complicates the switching sequence, is also discussed. The proposed schemes are completely free of the approximation errors inherent in the presently used LDI-based design techniques. The resulting circuits have low sensitivities both to element-value variations and to parasitic capacitances.

Time, frequency, and z-domain modified nodal analysis of switched-capacitor networks

Abstract: A rigorous and general derivation of the modified nodal equations needed for a time, frequency and z -domain analysis of multiphase switched-capacitor networks is given. Also a general equivalent circuit for switched-capacitor networks is derived. This technique allows to handle continuous coupling, piecewise-constant inputs as well as continuous inputs. These results can be used to adapt existing circuit analysis programs, based on modified nodal analysis, for efficient simulation of switched-capacitor networks.

Switched-capacitor filters using the LDI and bilinear transformations

Abstract: A relationship between a lossless discrete integrator (LDI) transformed inductor and a bilinear transformed inductor is presented. By applying this simple relationship, switched-capacitor (SC) filters using LDI structures can be used to realize bilinear transformed transfer functions, thus eliminating termination errors that usually exist in SC filters.

Class E high-efficiency switching-mode tuned power amplifier with only one inductor and one capacitor in load network-approximate analysis

Abstract: A class E high-efficiency switching-mode tuned power amplifier can be realized with only one inductor and one capacitor in the load network; previously published class E circuits contained at least two inductors and two capacitors. Switch conduction duty ratio and network loaded Q cannot be chosen independently as they can in the circuits published previously. This simplified circuit is appropriate for applications in which the harmonic content and the phase-modulation noise of the output are not important criteria, e.g. in providing RF energy for heating, for generation of sparks, arcs, or plasmas, for communications jamming, or for input drive to a higher power stage; or to a rectifier so that the entire circuit functions as a high-efficiency DC/DC converter. Experimental results and an approximate analysis are given; the two are in good-to-fair agreement.

Micropower Switched Capacitor Biquadratic Cell

Abstract: A very low power biquadratic SC filter section designed for LF or FLF structures has been developed using improved CMOS invertors together with a three phase clocking sequence. The integrated circuit achieves 66 dB dynamic range and less than 5 ?W power dissipation with a 32 kHz sampling frequency and a 3 V supply.

Induction generator system with switched capacitor control

Abstract: An electric power generator system including a switched capacitor controlled induction generator adapted to provide power at a regulated voltage and frequency. The system is adapted for autonomous operation for delivery of power with unity power factor to an external power grid.

Analysis and synthesis of switched-capacitor state-variable filters

Abstract: The design and analysis of switched-capacitor filters of the state variable or "leapfrog" type is presented in which the sampling rate may be as low as twice the highest frequency of interest. The effects due to the sampled data nature of the signals are fully taken into account and an exact synthesis is derived. This allows the sampling rate to be treated as a design parameter which Influences the maximum attenuation level in the stopband and the required capacitance ratios.

Offset compensation for switched capacitor integrators

Abstract: An integrator circuit utilizing an operational amplifier and switched capacitor elements in place of resistors in such a manner as to provide compensation for voltage offsets present in the operational amplifier resulting in an output voltage free from the effects of voltage offsets inherent in operational amplifiers.

Parasitic compensated switched capacitor circuits

Abstract: A parasitic-insensitive switched capacitor circuit is presented which can functionally replace the `toggle-switched? capacitor. Its properties are established via an inverting integrator application. A related parasitic-insensitive realisation is also shown for a noninverting integrator, which can provide a 3/2 clock period transmission delay.

Class AB CMOS amplifier micropower SC filters

Abstract: Properly biased CMOS invertors may be used as amplifiers in switched-capacitor filters. They are capable of fast settling and low noise at very low power. The principle of operation and three possible implementations are described.

The adjoint switched capacitor network and its application to frequency, noise and sensitivity analysis

Abstract: Given a linear network of capacitors, periodically controlled switches and sources we derive its adjoint network and show how it can be used to reduce the computational complexity of the frequency, noise and sensitivity analysis. The construction of the adjoint switched capacitor circuit turns out to be quite simple, even for switched capacitor networks with more than two phases or with a continuous input-output path. Moreover this construction can be performed equivalently in the time domain or on the equivalent circuit. In order to facilitate the implementation in a computer-aided-design program all derivations are performed in the modified nodal analysis formulation (MNA).

Switched capacitor temperature independent bandgap reference

Abstract: A temperature stable bandgap voltage reference source utilizing two substrate bipolar transistors biased at different emitter current densities is provided. Switched capacitors are used to input the V be and the ΔV be of the transistors (NTC and PTC voltages, respectively) into an amplifier to provide a reference voltage proportional to the weighted sum of the PTC and NTC voltages. Proper selection of the ratio of the switched capacitors renders the reference voltage substantially independent of temperature. In a modified form of the reference, the reference amplifier is implemented by an auto-zeroed operational amplifier which uses switched capacitor techniques and an integrated capacitor to achieve the auto-zeroing function.

Switched capacitor precision current source

Abstract: A switched capacitor precision current source uses a capacitance to store a predetermined charge in response to a clock to provide an average current proportional to the frequency of the clock and the predetermined charge. The average current is useful for generating bias voltages for N channel and P channel current sources.

An integrated single-chip PCM voice codec with filters

Abstract: A new single-chip monolithic compressed/expanded (companded) pulse-code modulation (PCM) coder/decoder (codec) is described. The associated switched-capacitor filters and reference voltage are also implemented on the chip, using a silicon-gate CMOS process. The DAC and ADC used incorporate a binary-weighted capacitor array and a string of equal-valued resistors. The circuit operators from a/spl plusmn/5 V supply and it consumes 65 mW in normal operation and 5 mW in the power-down condition. The implementation of the critical circuits in CMOS technology is discussed in detail.

Switched-capacitor source resistor simulation circuit

Abstract: An integratable circuit that simulates a source resistor comprises first and second nodes for connection to a voltage source and a virtual ground, respectively; a first integrated capacitor C1; and switch means operative for alternately electrically connecting C1's top and bottom plates to the first node and ground, respectively, and to ground and the second node, respectively, during first and second non-overlapping time periods in each time interval T for charging C1 to the source voltage and discharging C1 into the second node, respectively, where T is the time interval between adjacent second time periods and f=1/T is the switching frequency for C1. The switch means also operates for making similar connections to plates of second and third capacitors C2 and C3 in different time periods of ones of successive time intervals T, both C2 and C3 sampling a source voltage in synchronism with sampling by C1 during adjacent time intervals and holding a charge voltage for a time interval T prior to being discharged into the second node. The circuit simulates a source resistor when the first node is electrically connected to the output terminal of a voltage source that is connected to ground. This circuit configuration simulates a bilinear source resistor when the capacitances are the same values and the circuit is characterized by the bilinear transformation.

Switched-capacitor filter circuit having at least one simulated inductor and having a resonance frequency which is one-sixth of the sampling frequency

Abstract: A switched-capacitor filter circuit having at least one simulated inductor and having a resonance frequency which is one-sixth of the sampling frequency as pulse-controlled switches co-operatively operable for connecting a first capacitor to a pair of input terminals during a first clock phase and simultaneously connecting a second capacitor to the output of an inverting integration circuit, followed by discharge of the first capacitor to a capacitor in the integration circuit during a second clock pulse phase, followed by a third clock pulse phase during which the first capacitor is charged from the output of the integration circuit and the second capacitor is simultaneously connected to the pair of input terminals and during a fourth clock pulse phase the second capacitor discharges to the capacitor in the integration circuit.

A single-chip CMOS PCM codec with filters

Abstract: A complete PCM codec using charge redistribution and switched-capacitor techniques will be described. The device is implemented in a two-level polysilicon CMOS technology using 23.4 mm/SUP 2/ of active area. It features all the required transmission filters needed for telephony, two on-chip voltage references, TTL compatible digital interfaces, and low-power dissipation. The architecture of the chip allows asynchronous operation, a variable PCM data rate from 100 kbit/s to 4.096 Mbit/s, /spl mu//A law operation via pin selection, and gain selection at either of two levels in each direction.

A single-chip CMOS CODEC with switched-capacitor filters

Abstract: A single-chip CMOS codec with filters has been developed using charge redistribution and switched-capacitor techniques. Its features are ~30 mm/SUP 2/ small chip area, 35 mW low power dissipation, and small 16 pin package. These are achieved with novel analog circuit techniques for A/D and D/A conversions and clock generation. Measured transmission characteristics meet the system requirements.

Simplified MOS switched capacitor ladder filter structures

Abstract: A general technique for time-sharing amplifiers to reduce die area in switched capacitor ladder filters is described and illustrated with a fifth-order elliptic low-pass ladder filter requiring only three operational amplifiers. Techniques for synthesizing filters with maximum passband accuracy in the presence of parasitic capacitances are presented, and verified with two versions of the same fifth-order design integrated in a standard NMOS process. Passband accuracies of better than 0.1 dB have been achieved using only 0.3 pF unit-sized capacitors. The dynamic range is 75 dB.

Switched-capacitor pseudo-n-path filter

Abstract: A switched capacitor pseudo-N-path filter stage includes an analog integrator circuit having an input, an output, and a feedback capacitor connected between the input and the output. A plurality of storage capacitors are connected across the feedback capacitor and an input capacitor is provided. The feedback capacitor and storage capacitors form an analog random access memory. A switching circuit selectively connects the input capacitor across electrical ground and between an input signal and the input of the integrator circuit, and also selectively connects the feedback capacitor and the storage capacitors between electrical ground and the output of the integrator circuit. In this manner, the input signal is filtered as the input capacitor samples the input signal and the charge on the input capacitor is circulated through the feedback capacitor and the storage capacitors.

A single-chip CMOS filter/codec

Abstract: A second generation LSI codec has been implemented. In this chip, switched-capacitor filters, a charge redistribution encoder and decoder, voltage references, a signaling logic circuit, and all necessary functions for voice-PCM conversion are integrated. The authors describe the codec and summarizes its characteristics.

A comprehensive procedure for the design of cascaded switched-capacitor filters

Abstract: A complete set of design equations is given for first-order and biquadratic transfer functions in the z -domain. These equations are derived directly from the first- and second-order transfer functions in the s -domain. Consequently no new approximation for a prewarped set of cutoff frequencies is required. A step-by-step design procedure for SC filters follows. The sampling-conditions for input and output signals and for cascading are also discussed.