Showing papers on "Switched capacitor published in 2003"

Behavioral modeling of switched-capacitor sigma-delta modulators

Abstract: This paper presents a complete set of blocks implemented in the popular MATLAB SIMULINK environment, which allows designers to perform time-domain behavioral simulations of switched-capacitor (SC) sigma-delta (/spl Sigma//spl Delta/) modulators. The proposed set of blocks takes into account most of the SC /spl Sigma//spl Delta/ modulator nonidealities, such as sampling jitter, kT/C noise, and operational amplifier parameters (white noise, finite DC gain, finite bandwidth, slew rate and saturation voltages). For each block, a description of the considered effect as well as all of the implementative details are provided. The proposed simulation environment is validated by comparing the simulated behavior with the experimental results obtained from two actual circuits, namely a second-order low-pass and a sixth-order bandpass SC /spl Sigma//spl Delta/ modulator.

A triple-mode continuous-time /spl Sigma//spl Delta/ modulator with switched-capacitor feedback DAC for a GSM-EDGE/CDMA2000/UMTS receiver

Abstract: Time jitter in continuous-time /spl Sigma//spl Delta/ modulators is a known limitation on the maximum achievable signal-to-noise-ratio (SNR). Analysis of time jitter in this type of converter shows that a switched-capacitor (SC) feedback digital-to-analog converter (DAC) reduces the sensitivity to time jitter significantly. In this paper, an I and Q continuous-time fifth-order /spl Sigma//spl Delta/ modulator with 1-bit quantizer and SC feedback DAC is presented, which demonstrates the improvement in maximum achievable SNR when using an SC instead of a switched-current (SI) feedback circuit. The modulator is designed for a GSM/CDMA2000/UMTS receiver and achieves a dynamic range of 92/83/72 dB in 200/1228/3840 kHz, respectively. The intermodulation distance IM2, 3 is better than 87 dB in all modes. Both the I and Q modulator consumes a power of 3.8/4.1/4.5 mW at 1.8 V. Processed in 0.18-/spl mu/m CMOS, the 0.55-mm/sup 2/ integrated circuit includes a phase-locked loop, two oscillators, and a bandgap.

Analysis of switched-capacitor common-mode feedback circuit

Abstract: A detailed analysis of the dc behavior of switched-capacitor common-mode feedback circuit (SC-CMFB) is presented. A mathematical model, useful for analysis, is developed and the expressions for the output common-mode (CM) voltage, with and without considering the charge injection of switches and leakage currents, are derived. Further, the expression for dc CM settling time, is presented. The effect of parasitic capacitances, dc CM gain, charge injection error, and leakage currents, on the steady-state value of the dc CM voltage is analyzed and design guidelines to minimize these errors are presented. Finally, an improved version of the SC-CMFB circuit is analyzed. This circuit has very low errors due to charge injection and leakage currents and settles much faster than the traditional SC-CMFB circuit.

Transformerless DC-DC converters with a very high DC line-to-load voltage ratio

Abstract: By splitting the output capacitor of a basic boost converter, and combining the resulting capacitors with the main switch in the form of a switched-capacitor circuit, a new step-up structure is realized. Without using a transformer, a high line-to-load DC voltage ratio is obtained. An output filter is added as usual in boost converters for getting a free-ripple output. The circuit compares favorably with a quadratic boost converter as regarding the count of devices and efficiency, even if it presents a lower DC gain. A DC analysis of the novel converter is presented. Experimental and simulation results confirm the theoretical expectations. By increasing the number of capacitors in the switched-capacitor circuit, higher gains are obtained. Versatility, high voltage gain and a good transient response are the features of the proposed converter.

Ground bounce in digital VLSI circuits

Abstract: This paper is concerned with the analysis and optimization of the ground bounce in digital CMOS circuits. First, an analytical method for calculating the ground bounce is presented. The proposed method relies on accurate models of the short-channel MOS device and the chip-package interface parasitics. Next the effect of ground bounce on the propagation delay and the optimum tapering factor of a multistage buffer is discussed and a mathematical relationship for total propagation delay in the presence of the ground bounce is obtained. Effect of an on-chip decoupling capacitor on the ground bounce waveform and circuit speed is analyzed next and a closed form expression for the peak value of the differential-mode component of the ground bounce in terms of the on-chip decoupling capacitor is provided. Finally, a design methodology for controlling the switching times of the output drivers to minimize the ground bounce is presented.

Spatio-temporal filter and method

Abstract: A system, apparatus and methods are disclosed for the spatial and temporal processing of time dependant array data using analog signal processors. In one embodiment, a programmable array of switched capacitors is used to provide tunable parameters for controlling the desired processing of input data streams. The switched capacitor implementation of a spatial filter provides a massively parallel device that can be programmed to perform isotropic and spatially-oriented anisotropic filtering with low power demands. The system further includes the ability to combine differently filtered output streams with independent multiplicative weights. In another embodiment, the nonlinear spatio-temporal motion energy of a two-dimensional image stream data is computed. The spatial-temporal filter is able to combine multiple analog filters, both spatial and temporal, to perform complex spatial-temporal filtering operations implemented by Gaussian kernel filtering chips. It enables the use of analog spatial-temporal filtered data provided by the chip for computing scene motion energy.

Boost converter with high voltage gain using a switched capacitor circuit

Abstract: An integrated boost switched-capacitor (SC) converter able to step-up the line by ten times is presented. It is formed by a SC-circuit containing three capacitors and a boost stage. The two power stages are not connected in cascade, but they are integrated for achieving an overall high efficiency. The SC-circuit allows for a steep voltage ratio; for efficiency's purpose, it is not regulated. The boost stage gives the line and load regulation, using a classical PWM control. The theoretical results based on an energy-balance approach and simulation using the exact cyclical differential equations of the converter are confirmed by the experimental results on a prototype of 35 W power.

Modern Filter Design: Active RC and switched capacitor

Abstract: Originally published in 1981, Modern Filter Design remains a classic statement of the principles underlying the analysis and design of active RC and switched capacitor filters. Among other topics, the authors discuss the design of continuous-time, second order active sections (biquads), various measures of sensitivity, and the basic properties and classification of continuous-time and sampled data systems, together with filter transfer functions and approximations.

Switched capacitor circuit with reduced common-mode variations

Abstract: A circuit with a common-mode dual output includes a feedback circuit connected to alternate the states of the dual output between an average output level and a desired common-mode level. The difference between the average and desired levels is proportional to a signal offset level. An impedance matching circuit is connected to the feedback circuit to adjust the signal offset level.

Circuit and a method for controlling the bias current in a switched capacitor circuit

Abstract: A tunable constant GM circuit allows to compensate for temperature and process variations with high precision by correspondingly adjusting a resistance value and/or the ratio of transistor widths. Thus, in switched capacitor circuits the frequency behaviour, such as the settling time, may be controlled by providing a compensated bias to the transconductance amplifiers typically used in these circuits.

Low power, high SNR, high order delta sigma modulator stage having integrators with pipelined cross coupled input circuits

Abstract: In a high order delta sigma modulator stage having integrators with pipelined cross coupled input circuits, the processing delay between an upstream integrator and a downstream integrator is decreased from a full cycle of a clock used to control the high order delta sigma modulator stage to a half cycle of the clock, while the processing delay between a quantizer and a portion of a digital-to-analog converter that provides feedback to the upstream integrator is increased by a half cycle of the clock. This configuration: (1) eliminates poles from the transfer function that defines processing of a signal by the high order delta sigma modulator stage, (2) reduces the power consumed by the high order delta sigma modulator stage for a given settling time requirement, (3) facilitates reducing the size of the summing junction switches in the high order delta sigma modulator stage to decrease distortions due to charge injections, and (4) allows a reference signal voltage, which is coupled to a cross coupled feedback switched capacitor network in the integrators, to be set equal to one of two power supply voltages for the high order delta sigma modulator stage, thereby further reducing the power consumed by the delta sigma modulator.

Computer methods for switched circuits

Abstract: This paper presents a state-of-the-art review of the recent advances in computer methods for analysis and design of switched circuits in both time and frequency domains. It also presents new research results on time-domain analysis and sensitivity of switched nonlinear circuits, time- and frequency-domain statistical analysis of switched linear and nonlinear circuits, and efficient modeling and analysis of clock feedthrough and charge injection in switched linear circuits. In time-domain analysis, the modeling of switches and its effect on the simulation of switched circuits are investigated. Formulation methods for these circuits are examined. Inconsistent initial conditions arising from ideal switching are investigated and numerical methods that derive the consistent initial conditions are examined. Sampled-data simulation (SDSIM) of switched linear circuits including clocked sigma-delta modulators is investigated. SDSIM is extended to switched nonlinear circuits. Time-domain sensitivity of switched linear and nonlinear circuits is analyzed using SDSIM. Efficient time-domain statistical analysis of switched linear and nonlinear circuits is introduced, and their effectiveness is assessed using Monte Carlo simulation. Methods that compute the effect of the clock jitter of periodically switched linear (PSL) circuits are examined. Time-domain noise analysis of PSL circuits is investigated. In frequency-domain analysis, exact frequency analysis of multiphase PSL circuits is reviewed. Sensitivity analysis of these circuits is examined in detail. Adjoint network theory and its usefulness in noise and sensitivity analysis of switched linear circuits are studied. Group delay of PSL circuits is investigated briefly. Efficient modeling and analysis of clock feed-though and charge injection of PSL circuits are introduced. Distortion and sensitivity of periodically switched nonlinear circuits with mild nonlinearities are investigated. Finally, frequency-domain noise analysis of PSL circuits is examined.

A /spl Sigma/-/spl Delta/ fractional-N frequency synthesizer using a wideband integrated VCO and a fast AFC technique for GSM/GPRS/WCDMA applications

Abstract: A fractional-N frequency synthesizer (FNFS) in a 0.5-/spl mu/m SiGe BiCMOS technology is implemented. In order to operate wideband frequency range, a switched capacitor bank LC tank VCO and an adaptive frequency calibration (AFC) technique are used. A 3-bit 4th order /spl Sigma/-/spl Delta/ modulator is used to reduce out-of-band phase noise and to meet a frequency resolution of less than 3Hz as well as agile switching time. The experimental results show -80dBc/Hz in-band phase noise within the loop bandwidth of 25 kHz and -129dBc/Hz out-of-band phase noise at 400kHz-offset frequency. The fractional spurious is less than -70dBc/Hz at 300kHz offset frequency and the reference spur is -75dBc/Hz. The lock time is less than 150 /spl mu/s. The proposed synthesizer consumes 19.5 mA from a single 2.8-V supply voltage and meets the requirements of GSM/GPRS/WCDMA applications.

Voltage controlled oscillators with selectable oscillation frequencies and methods for adjusting the same

Abstract: Voltage controlled oscillators include an amplifier that generates an oscillation output signal having an oscillation frequency based on an applied inductance and capacitance. An inductor coupled to the amplifier applies the inductance. A switched capacitor circuit includes a plurality of switches and capacitors selectably coupled to the amplifier through respective ones of the switches. A switched varactor circuit includes a plurality of switches and varactors selectably coupled to the amplifier through respective ones of the switches. The capacitances of the varactors are responsive to an applied control voltage. A control circuit is configured to select ones of the switches of the capacitor circuit and of the varactor circuit and to provide a selected control voltage to the varactor circuit to apply a desired capacitance to the amplifier.

Adc having chopper offset cancellation

Abstract: A circuit includes a differential amplifier circuit and a chopper offset cancellation circuit chopping a switched capacitor circuit. The offset cancellation mechanism including input cross-coupled switches coupled between a differential capacitive element and the amplifier circuit inputs and output cross-coupled switches coupled between the differential capacitive element and the amplifier circuit outputs for swapping the amplifier circuit inputs and outputs to cancel shpper offset. The circuit further including an input switch network coupled between differential input signal terminal sand the amplifier positive and negative inputs external to the integrating feedback configuration for swapping the differential input signal terminal connections to the amplifier positive and negative inputs. Moreover, the circuit including an output switch network coupled between differential output signal terminals and the amplifier positive and negative outputs external to the integrating feedback configuration.

Switched-capacitor amplifier and analog interface circuit for charge coupled element adopting the same

Abstract: In the hold phase, two negative feedback circuits constituted by the negative feedback capacitors 6 p and 6 m and two positive feedback circuits constituted by positive feedback capacitors are provided between an input terminal and an output terminal of an operational amplifier. Here, in a sampling phase before a hold phase, charges according an input signal V1 p is stored in each of the capacitors, and charges according to an input signal V1 p are stored in each of the capacitors. As a result, a gain of the switched capacitor amplifier circuit is derived from (Ca+C)/(Ca−Cx) wherein Ca indicates an electrostatic capacitance of the negative feedback capacitors, and Cx indicates an electrostatic capacitance of the positive feedback capacitors, and thus the gain can be increased without significantly increasing an electrostatic capacitance ratio.

High resolution, high speed, low power switched capacitor analog to digital converter

Abstract: An analog to digital converter includes first and second converter segments having respective first and second arrays of binary weighted capacitors. Each capacitor of the first segment has a first electrode connected to a first common node and a second electrode connected through respective switches to one of a first reference voltage terminal and an input terminal. Each capacitor of the second segment has a first electrode connected to a second common node and a second electrode connected through respective switches to one of the first reference voltage terminal and the input terminal. The converter includes a coupling capacitor connected between the first and second common nodes and capacitance means connected between the first common node and a reference voltage terminal. The coupling capacitor and capacitance means have capacitances, C s and C ATT respectively, that substantially satisfy the relationship: (2 p −1)·C s −C ATT =2 p ·C, where p is the number of bits coded in the first converter segment and C is the unit capacitance.

Input filter for A.C. motor phase current sensing

Abstract: An input filter to block noise components of motor phase current used as an input signal for a PWM motor controller. The input filter includes an integration circuit driven by a triggering signal at a frequency which is twice the frequency of operation of the inverter. In one embodiment, a first integrator is coupled directly to the motor drive current signal, and a second integrator is coupled to the motor drive current signal through a circuit which introduces a delay equal to the period of the triggering signal. The difference between the outputs of the integrators is then sampled at the triggering signal frequency. In a second embodiment, a voltage-to-time converter generates a first ramp representing the integral of the phase current signal during a first triggering interval, and a second ramp representing the integral of a reference signal, is subtracted from the value of the first ramp during a second triggering interval until value of integrator output returns to zero. In a third embodiment, a switched capacitor integration circuit is operated by a high speed clock synchronized to the triggering signal. The integrator output is sampled at the end of each triggering period and coupled to an analog to digital converter.

Switched-capacitor structures with enhanced isolation

Abstract: Switched-capacitor structures are provided that reduce distortion and noise in their processed signals because they increase isolation between structural elements and ensure that selected elements are securely turned off in one mode and quickly turned on in another mode.

A 1-/spl mu/A front end for pacemaker atrial sensing channels with early sensing capability

Abstract: A low-power front end for a pacemaker atrial sensing channel based on level detection is presented. The very tight system specifications in terms of power consumption and output noise, the need to operate with a supply voltage decreasing from 2.8 to 2 V during the battery lifetime, and additional functionalities with respect to standard front ends, like gain programmability and early sensing, make the design of this system a challenge. The front end includes a preamplifier and a third-order switched capacitor filter, and it is fabricated in a 0.8 /spl mu/m CMOS technology. It features a 1 /spl mu/A current consumption at a supply voltage of 2.7 V, and an input referred total noise of 6.9 /spl mu/V/sub rms/.

Architecture for an algorithmic analog-to-digital converter

Abstract: An algorithmic analog-to-digital converter (ADC) includes a sample-and-hold circuit and an ADC processing unit operating in parallel and sharing a single operational amplifier. The ADC processing unit includes an MDAC with a switched capacitor topology and a sub-ADC. The ADC processing unit is clocked by an internal clock that is N times faster than the sample-and-hold clock. Each cycle is further sub-divided into two phases. During one phase the capacitors are coupled to a residue or sampled voltage provided by the MDAC, and during another phase the capacitor are coupled to a reference voltage determined by the switch control signals generated by the sub-ADC. A set of data bits is generated by the ADC processing unit during each ADC clock cycle. The N sets of data bits are added to generate the digital output stream.

Switched capacitor voltage reference circuits using transconductance circuit to generate reference voltage

Abstract: A switched capacitor voltage reference circuit that has a transconductance circuit that receives the output of the amplifier, and then outputs a current that depends on its input voltage. This may be accomplished using a charge pump that is controlled by the amplifier output. The transconductance circuit provides a reference voltage at the output terminal of the switched capacitor generation circuit. A capacitor capacitively couples the output terminal of the switched capacitor circuit to the inverting terminal of the amplifier during the generation phase. By adjusting the capacitances of the various capacitors, the level and temperature dependence of the generated reference voltage may be controlled. Also, the charge pump often allows for reference voltages that are greater than the supply voltage.

Low-voltage low-power fast-settling CMOS operational transconductance amplifiers for switched-capacitor applications

Abstract: This paper presents a new fully differential operational transconductance amplifier (OTA) for low-voltage and fast-settling switched-capacitor circuits in digital CMOS technology. The proposed two-stage OTA is a hybrid class A/AB that combines a folded cascode as the first stage with active current mirrors as the second stage. It employs a hybrid cascode compensation scheme, merged Ahuja and improved Ahuja style compensations, for fast settling.

A continuous-time sigma-delta modulator with switched capacitor controlled current mode feedback

Abstract: This paper presents a previously unpublished technique for the reduction of the sensitivity to clock jitter in continuous-time sigma-delta modulators. Therefore, the main clock jitter source, the feedback digital-to-analog converter, is implemented by using a sloping feedback pulse-form, which is generated by a transistor current source and a circuit to generate the slope. In this first implementation, a third-order continuous-time modulator has been designed, achieving 10 bits of resolution and consuming only 250/spl mu/W from a 1.5V supply, while the jitter sensitivity could be remarkably reduced.

Capacitor matching insensitive 12-bit 3.3 MS/s algorithmic ADC in 0.25 /spl mu/m CMOS

Abstract: This paper presents a novel circuit architecture for the accurate realization of the basic 1.5-bit ADC stage common to switched capacitor algorithmic and pipelined ADCs. A floating buffer is proposed which enables the accurate addition of signal voltages without requiring precision components. 14-bit ADC linearity is demonstrated with uncharacterized metal-metal capacitors without the need for calibration or trimming. A prototype 12-bit 3.3 MS/s algorithmic ADC in 0.25 /spl mu/m standard CMOS is described. The power FOM is 1.2 pJ/conversion and the area FOM is 31 nm/sup 2//conversion - well below previously reported figures for algorithmic ADCs.

Need to revise switched capacitor controls on feeders with distributed generation

Abstract: This paper addresses the need to review switched capacitor settings on radial distribution feeders prior to installing distributed generation (DG). Bringing a DG on line without conducting an analysis may result in over-voltages or capacitors switching OFF, depending of the type of controls. A simple case of a feeder with a single DG and switched capacitor with different controls is examined in detail, and is illustrated with a numerical example. The analysis alerts electric distribution engineers to review and reset capacitor switching preset values, if necessary, prior to DG installation.

Response of a simple dependent switched capacitor circuit to a pulse-train input

Abstract: This paper studies a simple nonautonomous circuit consisting of an RLC resonator, a dependent switch and a periodic pulse-train input. The circuit can exhibit chaotic behavior if an equidistant pulse-train input is applied. The dynamics can be analyzed by a mapping procedure based on a one-dimensional (1-D) return map focusing on the moments when the input is applied. If the periodic pulse-train input is nonequidistant, the dynamics can be analyzed by a composite of different 1-D return maps corresponding to different pulse intervals. We show typical chaotic and periodic phenomena in this case. Using a simple test circuit, we can verify typical phenomena in the laboratory.

Design and analysis of power-CMOS-gate-based switched-capacitor DC–DC converter with step-down and step-up modes

Abstract: A unified multi-stage power-CMOS-transmission-gate-based quasi-switched-capacitor (QSC) DC–DC converter is proposed to integrate both step-down and step-up modes all in one circuit configuration for low-power applications. In this paper, by using power-CMOS-transmission-gate as a bi-directional switch, the various topologies for step-down and step-up modes can be integrated in the same circuit configuration, and the configuration does not require any inductive elements, so the IC fabrication is promising for realization. In addition, both large-signal state-space equation and small-signal transfer function are derived by state-space averaging technique, and expressed all in one unified formulation for both modes. Based on the unified model, it is all presented for control design and theoretical analysis, including steady-state output and power, power efficiency, maximum voltage conversion ratio, maximum power efficiency, maximum output power, output voltage ripple percentage, capacitance selection, closed-loop control and stability, etc. Finally, a multi-stage QSC DC–DC converter with step-down and step-up modes is made in circuit layout by PSPICE tool, and some topics are discussed, including (1) voltage conversion, output ripple percentage, and power efficiency, (2) output robustness against source noises and (3) regulation capability of converter with loading variation. The simulated results are illustrated to show the efficacy of the unified configuration proposed. Copyright © 2003 John Wiley & Sons, Ltd.

Switched capacitor power converter

Abstract: A switched-capacitor power converter includes capacitive elements and switching elements configurable to provide a non-integer step-up or non-integer step-down voltage conversion.