Showing papers on "Topology (electrical circuits) published in 1999"

A Survey of Virtual Topology Design Algorithms for Wavelength Routed Optical Networks

Abstract: In the past few years, there has been growing interest in wide area ``All Optical Networks'''' with {\em wavelength division multiplexing\/} (WDM), using {\em wavelength routing}. Due to the huge bandwidth inherent in optical fiber, and the use of WDM to match user and network bandwidths, the wavelength routing architecture is an attractive candidate for future backbone transport networks. A {\em virtual topology\/} over a WDM WAN consists of clear channels between nodes called {\em lightpaths}, with traffic carried from source to destination without electronic switching ``as far as possible'''', but some electronic switching may be performed. Virtual topology design aims at combining the best of optical switching and electronic routing abilities. Designing a virtual topology on a physical network consists of deciding the lightpaths to be set up in terms of their source and destination nodes and wavelength assignment. In this survey we first describe the context and motivations of the virtual topology design problem. We provide a complete formulation of the problem, describe and compare the formulations and theoretical results as well as algorithms, heuristics and some results in the current literature in the field. The reconfigurability issue, which is another attractive characteristic of optical networks, is also discussed and the literature surveyed. This survey is restricted to transport networks with wavelength routing. Similar virtual topology problems also arise in multihop broadcast local area optical networks, but this work does not directly apply to them and corresponding literature is not included in this survey. This survey also relates to the design of a static topology, not one in which individual lightpaths are set up and torn down in response to traffic demand.

Diagnosis of continuous valued systems in transient operating regions

Abstract: The complexity of present day embedded systems (continuous processes controlled by digital processors), and the increased demands on their reliability motivate the need for monitoring and fault isolation capabilities in the embedded processors. This paper develops monitoring, prediction, and fault isolation methods for abrupt faults in complex dynamic systems. The transient behavior in response to these faults is analyzed in a qualitative framework using parsimonious topological system models. Predicted transient effects of hypothesized faults are captured in the form of signatures that specify future faulty behavior as higher order time-derivatives. The dynamic effects of faults are analyzed by a progressive monitoring scheme till transient analysis mechanisms have to be suspended in favor of steady state analysis. This methodology has been successfully applied to monitoring of the secondary sodium cooling loop of a fast breeder reactor.

Apparatus and method for unilateral topology discovery in network management

Abstract: A system for reducing the cost of network managment by using a proxy agent and subchannel communications so fewer SNMP licenses and fewer protocol stacks are needed. Subchannel communication is achieved in a plurality of different embodiments. Embodiments having single subchannel transceivers, multiple transceivers, single multiplexer and multiple multiplexers are disclosed. An NMS process using routing table CRC to automatically detect when the NMS topology information is incorrect and automated topology discovery is disclosed. A process for automated discovery of redundant cables during automated topology discovery is disclosed.

X-band RF MEMS phase shifters for phased array applications

Abstract: In this work, development of a low-loss radio frequency (RF) microelectromechanical (MEMS) 4-bit X-band monolithic phase shifter is presented. These microstrip circuits are fabricated on 0.021-in-thick high-resistivity silicon and are based on a reflection topology using 3-dB Lange couplers. The average insertion loss of the circuit is 1.4 dB with the return loss >11 dB at 8 GHz. To the best of our knowledge, this is a lowest reported loss for X-band phase shifter and promises to greatly reduce the cost of designing and building phase arrays.

A new soft-switched quasi-single-stage (QSS) bi-directional inverter/charger

Abstract: A new soft-switched quasi single-stage (QSS) bidirectional inverter/charger topology is proposed in this paper. It realizes seamless four-quadrant operation in inverter mode, and rectifier operation with unity power factor in charger mode. Single stage power conversion, standard half-bridge connection of devices, soft-switching for all the power devices, low conduction loss, simple center-aligned PWM control, and high efficiency are among the salient features. The principles of circuit operation, PWM control and synthesis, and topological extension are discussed in this paper. The experimental results on a 3 kVA prototype (12 V DC to and from 110 V AC) are also presented.

Method and apparatus for determining accurate topology features of a network

Abstract: A monitoring system (switches A and B) for determining topology features of a network includes methods for creating a topology map of the network by: obtaining a list of managed network devices; identifying trunk ports, link channel ports, and trunk channel ports; identifying link port (2) and node ports; determining connections between the ports (1-8); storing the collected information; and displaying the network topology. The system also includes methods for obtaining information regarding the devices and machines connected to the network, including VLAN (a-h) and backplane information, router ARP table information, device interface information, and physical address information. Also, ports and/or devices are logically grouped for in order to provide more accurate topology information.

Design and performance evaluation of low-voltage/high-current DC/DC on-board modules

Abstract: The topology selection, design and performance evaluation of an on-board DC/DC converter, which delivers power from a 48-V input to a 1.2-1.65 V/70 A microprocessor load, are presented. It was shown that the symmetrical half-bridge topology with the current doubler and synchronous rectifiers is a suitable approach for this application. The measured full-load efficiency of a 200-kHz experimental half-bridge converter was higher than 82% in the entire output and input voltage range.

A neural network based space vector PWM controller for voltage-fed inverter induction motor drive

Abstract: A neural network based implementation of space vector modulation of a voltage-fed inverter has been proposed in this paper that fully covers the undermodulation and overmodulation regions linearly extending operation smoothly up to square wave. The neural network has the advantage of very fast implementation of SVM algorithm that can increase the converter switching frequency, particularly when a dedicated ASIC chip is used in the modulator. Two ANN-based SVM techniques have been validated: an indirect method with the help of a timer that generates the PWM waveforms from the command voltage vector at the input, and a direct method that synthesizes waveforms directly without any timer. The indirect method has been fully implemented and extensively evaluated in a volts/Hz controlled 5 hp, 60 Hz, 230 V induction motor drive. The performances of the drive with ANN-based SVM are excellent. The scheme can be easily extended to vector-controlled drive. The direct method, although has a simpler topology, needs very large training data and training time.

All-pass filters using a single current conveyor

Abstract: Current conveyors are unity gain active elements exhibiting high linearity, wide dynamic range and better high frequency performance compared with their voltage mode counterparts. In this study a set of single positive-type second generation current conveyor based all-pass filters is presented and a catalogue of canonical topologies is given with some properties in tabular form. In contrast with single topology presentations, 22 different topologies are presented which exhibit identical transfer functions but differ in the number of passive components, component matching constraints, possibility of gain adjustment and other properties.

Fiber channel topological structure and method including structure and method for raid devices and controllers

Abstract: System, apparatus and method for interconnecting computer devices define an interconnect topology maximizing performance and device availability in the event of a communication channel failure. Structure and method are particularly relevant and beneficial to a computer RAID disk interconnection topology for Fibre Channel connections to improve RAID array performance and data availability, but is not limited to such RAID systems, and other devices may be interconnected according to the structure and method of the invention. A topology having multiple dual-ported controllers configured in a tube topology is provided for a switchable configuration having a plurality of channels and an plurality of controllers arranged in a tube topology or structure. In the event of a channel failure for this structure, the load will be evenly distributed to the remaining controllers. One embodiment provides a data storage system having a plurality of storage devices each having first and second access ports, a plurality of communication channels, a controller controlling access by the plurality storage devices to the plurality of channels, where at least one of the devices is connected via the first access port to a first one of the channels and via the second access port to a second one of the channels, so that the one device may be accessed by the controller via either the first or second channels channel. Mathematical relationships between the and minimum number of devices for an automatically balanced system and the number of channels are described.

Design of an IGBT-based LCL-resonant inverter for high-frequency induction heating

Abstract: A power electronic inverter is developed for a high-frequency induction heating application. The application requires up to 160 kW of power at a frequency of 100 kHz. This power-frequency product represents a significant challenge for today's power semiconductor technology. Voltage source and current source inverters both using ZCS or ZVS are analyzed and compared. To attain the level of performance required, an LCL load-resonant topology is selected to enable ZVS close to the zero current crossing of the load. This mode of soft-switching is suitable to greatly reduce the IGBT losses. Inverter control is achieved via a phase locked loop (PLL). This paper presents the circuit design, modeling and control considerations.

A linear switched reluctance motor: converter and control

Abstract: The converter topology with a minimum number of power devices and control implementations to facilitate the pulsation-free force control of the linear switched reluctance machines are investigated for the first time in this paper. The minimization of the devices offers cost reduction, compact packaging, and enhanced overall reliability. With that in view, a topology with 3N/sub sc/+3 devices is chosen where N/sub sc/ is the number of sectors in the linear machine. The propulsion force with conventional control of single-phase excitation has high-commutation torque pulsation and it is overcome with a multiphase excitation strategy, proposed in this paper. Further, the proposed control strategy reduces the normal force pulsation. A systematic step-by-step design procedure of the switching strategy for the converter known as unipolar switching strategy, proportional plus integral current controller, and gating control strategy of a long linear switched reluctance machine is presented. Experimental correlation of the proposed converter arrangement and control strategy is presented with a 4.8 m-long linear switched reluctance machine in achieving the stated objectives.

A multistage amplifier technique with embedded frequency compensation

Abstract: A new multistage operational amplifier topology requires only N-2 embedded compensation networks for N gain stages. The compensation circuits do not load the output stage, and noninverting gain stages are not required as in previous multistage approaches. Consequently, high gain, wide bandwidth, fast slewing, and excellent power efficiency are achieved. A low-power resistance-capacitance compensation technique assures stability and fast settling over process, voltage, and temperature variations. Implemented in a 0.6-/spl mu/m n-well CMOS process, a single ended three-stage prototype dissipates 6.9 mW at 3.0 V with 102 dB gain, 47 MHz bandwidth, and 69 V//spl mu/s average slew rate with 40 pF load.

Integrated planar inductor scheme for multi-module interleaved quasi-square-wave (QSW) DC/DC converter

Abstract: Compact, high-efficiency, low-voltage and large-current DC/DC power converters with a fast transient slew rate are needed for future generation microprocessors. The interleaved quasi-square-wave (QSW) topology is a good candidate to improve their transient response significantly. Inductors are critical components in these converters. An integrated planar inductor scheme for multi-module interleaved QSW power converters is proposed. This integrated inductor utilizes the phase relationships of the currents in each module to integrate all the separate inductors for each module into one core, resulting in great reductions in the size and power losses of the inductor.

A general technique for derivation of average current mode control laws for single-phase power-factor-correction circuits without input voltage sensing

Abstract: This paper presents a general technique to derive average current mode control (CMC) laws without input voltage sensing to achieve high power factor for single-phase topologies operating in continuous conduction mode (CCM). The control laws are derived based on the steady-state input-output voltage relationships and the CCM large-signal averaged pulsewidth modulation (PWM)-switch model. Using this methodology, average CMC laws with linear PWM waveforms are discovered for commonly used single-phase power stage topologies such as boost, flyback, SEPIC, and buck/boost. Conventional three-loop-controlled average CMC converters can now be controlled with a two-loop architecture. Hardware results for a boost power factor correction (PFC) and simulation results for flyback, SEPIC, and buck/boost topologies verify operation. The small-signal models of the current loop and voltage loop are derived for the boost topology and are used for control loop design. Input current harmonic distortion measurements demonstrate improved performance compared to the conventional three-loop control technique.

A robust estimation method for topology error identification

Abstract: A pre-processing method that identifies both multiple topology errors and bad measurements is described. The method determines the branch statuses by testing the real and reactive power flow estimates of all the branches of the network, irrespective of their assumed statuses. The power flows are the state variables of two decoupled real and reactive power models that stem from both a detailed substation representation and a super-node modeling. They are estimated by means of the iteratively reweighted least-squares algorithm that implements the Huber M-estimator. The procedure is not prone to divergence problems, which is of great value in a real-time environment. The performance of the method is demonstrated on the IEEE-118 bus system.

An innovative technique for packaging power electronic building blocks using metal posts interconnected parallel plate structures

Abstract: Power electronics building blocks (PEBBs) are envisioned as integrated power modules consisting of power semiconductor devices, power integrated circuits, sensors, and protection circuits for a wide range of power electronics applications, such as inverters for motor drives and converters for power processing equipment. At the Center for Power Electronics Systems, we developed a topology for a basic building block-a two-switch two-diode half-bridge converter in totem-pole configuration with built-in gate-driver and protection circuitry, fiber-optic receiver/transmitter interface, and soft-switching capability. Based on the topology, a series of prototype modules, with 600 V, 3.3 kW rating, were fabricated using an innovative packaging technique developed for the program-metal posts interconnected parallel plate structure (MPIPPS). This new packaging technique uses direct attachment of bulk copper, not wire-bonding of fine aluminum wires, for interconnecting power devices. Electrical performance data of the packaged devices show that an air-cooled 15 kW inverter, operating from 400 V dc bus with 20 kHz switching frequency can be constructed by integrating three prototype modules, which is almost double what could be achieved with commercially packaged devices of the same rating.

Compact multiple output power supply

Abstract: A compact multiple output power supply which has a circuit architecture with distinct primary and secondary circuit domains. Within the secondary circuit domain, a distribution bus of relatively low constant voltage supplies power inputs to d.c.-to-d.c. converters providing regulated outputs and operating independently of each other. Because of the secondary circuit domain topology, surface mount components are made available in conjunction with relatively simple converter circuitry. Heat management within the compact housing of the power supply is achieved through the utilization of linear driven air flows in combination with employment of heat sinks extending to the heat sink configured cover of the housing. Additionally, the highest heat generation components are positioned rearwardmost within the driven air path.

Forward-flyback converter with current-doubler rectifier: analysis, design, and evaluation results

Abstract: Complete design-oriented steady-state analysis of the forward-flyback converter, with the current-doubler rectifier is provided. Advantages and disadvantages of this topology compared to the conventional forward converter are discussed. In particular, the transformer-secondary copper losses are evaluated. In addition, a step-by-step design procedure is given, Finally, experimental evaluation results obtained on a 3.3 V/50 A DC/DC converter prototype for the 40-60 V input-voltage range are presented.

Lossless current sensing in buck converters working with low duty cycles and high clock frequencies

Abstract: A buck converter having a synchronous rectifier topology that performs current sensing at the low-side switch and employs "valley current control" to terminate a discharging phase and commence a charging phase of the converter. The buck converter is able to withstand high operating frequencies and low duty cycles to produce a low output voltage from a given high input voltage.

Advanced Control of Active Filters in a Battery Charger Application

Abstract: In this thesis, a high performance battery charger for electric vehicles (EVs) is investigated. By including active power line conditioning capabilities in the battery charger, a viable concept for a fast charging infrastructure is obtained, beneficial both to the EV users and the power distributors. The thesis contains discussions on modelling aspects and design considerations for the proposed battery charger, based on a carrier wave modulated self commutated 2-level voltage source converter topology. Furthermore, model based controller synthesis is employed, and thorough analysis of the controller characteristics is given. Emphasis is put on the active filtering performance of the battery charger. The weaknesses of the model based control system in active filter applications are revealed, where especially the inherent phase deviation of the control system and the sensitivity to system parameters deteriorates the performance of the active filter. In order to overcome the deteriorating properties of the model based controller, a controller structure for active filters based on several integrators in multiple reference frames is proposed. It is shown, both theoretically and experimentally, that the proposed controller exhibits low sensitivity to system parameters and provides for complete compensation of the inherent phase deviation. The result is excellent conditioning performance of the proposed active filter controller in steady state.

A new high-frequency and high-efficiency electronic ballast for HID lamps: topology, analysis, design, and experimental results

Abstract: A new high-frequency and high-efficiency electronic ballast for high-intensity discharge (HID) lamps is presented. The ballast features an integral resonant ignitor, high efficiency, power regulation, and optional hot strike and fast warm-up capabilities. The ballast can operate virtually any lamp without acoustic arc resonance. The paper presents the topology, operation, analysis, design considerations, and experimental results obtained from a 70 W prototype.

System and method using level three protocol information for network centric problem analysis and topology construction of actual or planned routed network

Abstract: A method is provided for managing a computer network includes the step of providing respective router configuration information in executable form; producing respective Structured Router Objects (SROs) that are respectively associated with respective router configuration information and that respectively organize associated information in executable form in respective structures in electronic memory; and producing respective Single Protocol Topology (SPT) objects in electronic memory, each respectively associated with a different respective single protocol and each respectively interrelating SROs associated with the same respective single protocol.

SuperMix: A Flexible Software Library for High-Frequency Circuit Simulation, Including SIS Mixers and Superconducting Elements

Abstract: 'SuperMix" is a software library written to aid in the calculation and optimization of the signal and noise performance of high -frequency circuits, especially those including superconductors and superconducting tunnel junctions. Using this library, C++ programs can be written to simulate circuits of arbitrary size, complexity, and topology. The library includes an optimizer which can minimize an arbitrary error function by varying chosen circuit parameters. Using SuperMix, it is now possible to directly optimize an SIS receiver design to minimize the average noise temperature across the desired RF frequency band. including a full harmonic balance analysis at every frequency. point together with a full analysis of the IF amplifier circuit and its noise contribution.

Parallel HV mosfet high power stable amplifier

Abstract: A high power grounded-drain source follower RF amplifier circuit employs a high voltage MOSFET. The RF signal at the input is applied with respect to ground via an isolation transformer whose secondary feeds the signal between gate and source. The output is taken from the source with respect to drain, which is grounded. A 13.56 MHz 3 KW power amplifier topology with isolated RF input drive for each MOSFET die uses a pair of kilowatt power transistors or KPTs, in which there are multiple large area MOSFET dies, with the drain regions of the dies being formed over a major portion of the die lower surface. The drain regions are in direct electrical and thermal contact with the conductive copper flange. The source and gate regions are formed on the dies away from the flat lower surface. One or more pairs of multi-chip KPTs can be configured to design stable 2.5 KW, 5 KW and 10 KW RF plasma generators at 13.56 MHz. The generators employ a low pass/high pass filter arrangement (diplexer) at the output for low harmonic distortion and dissipative harmonic termination. The terminated high pass filter reduces the gate-to-source differential RF voltage and protects the MOSFETS from damage.

On the maximum number of finite transmission zeros of coupled resonator filters with a given topology

Abstract: This letter presents a rigorous proof of the maximum number of finite transmission zeros which can be achieved by a network of coupled resonators with a fixed topology matrix. Once the topology matrix is fixed, the number of finite transmission zeros cannot exceed this number regardless of the choice of the frequency-independent coupling coefficients M/sub ij/.

Modified asymmetrical ZVS half-bridge DC-DC converter

Abstract: A modification is proposed for the asymmetrical zero-voltage-switched (ZVS) half-bridge DC-DC converter topology that substantially changes the static transfer function and the voltage stress distribution within the converter power mesh. This modification allows the converter circuit to be optimised for higher efficiency and power density. It is also postulated that the modification with its corresponding benefits can be utilised in other complementary driven topologies. Although the asymmetrical H-B converter is inherently capable of ZVS switching, only the proper choice of parameters can insure ZVS in all modes of operation. The DC circuit analysis and design procedure for the power stage components are presented. Experimental results, in good agreement with the analysis, are presented for a 300 W converter operating at 500 kHz, with 5 VDC/60 Amp output, and 84% efficiency at 75 W/in/sup 3/.

On a lightwave network topology using Kautz digraphs

Abstract: In this paper, the properties of Kautz digraphs are studied to evaluate their suitability as topology for optical networks. The properties are compared to those of other topologies proposed in the literature and it has been shown these topologies have better performance in terms of queuing delay in a multihop network. For a given degree of each node and a given diameter of the network, a Kautz digraph supports more nodes than other topologies, like shufflenet or that of using a de Bruijn digraph, and seems to be an attractive design for the physical topology as well.

Persistent Currents on Networks

Abstract: We develop a method to calculate persistent currents and their spatial distribution (and transport properties) on graphs made of quasi-1D diffusive wires. They are directly related to the field derivatives of the determinant of a matrix which describes the topology of the graph. In certain limits, they are obtained by simple counting of the nodes and their connectivity. We relate the average current of a disordered graph with interactions and the noninteracting current of the same graph with clean 1D wires. A similar relation exists for orbital magnetism in general.