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Alberto Sangiovanni-Vincentelli

Researcher at University of California, Berkeley

Publications -  946
Citations -  47259

Alberto Sangiovanni-Vincentelli is an academic researcher from University of California, Berkeley. The author has contributed to research in topics: Logic synthesis & Finite-state machine. The author has an hindex of 99, co-authored 934 publications receiving 45201 citations. Previous affiliations of Alberto Sangiovanni-Vincentelli include National University of Singapore & Lawrence Berkeley National Laboratory.

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Book

Synthesis of Finite State Machines : Functional Optimization

TL;DR: Key themes running through the book are the exploration of behaviors contained in a non-deterministic FSM, and the representation of combinatorial problems arising in FSM synthesis by means of Binary Decision Diagrams (BDDs).
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Synthesis of software programs for embedded control applications

TL;DR: A software generation methodology is proposed that takes advantage of a restricted class of specifications and allows for tight control over the implementation cost, and exploits several techniques from the domain of Boolean function optimization.
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SMT-Based Observer Design for Cyber-Physical Systems under Sensor Attacks

TL;DR: A novel multi-modal Luenberger (MML) observer based on efficient Satisfiability Modulo Theory (SMT) solving is proposed and an efficient SMT-based decision procedure is developed able to reason about the estimates of the MML observer to detect at runtime which sets of sensors are attack-free, and use them to obtain a correct state estimate.
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A survey of third-generation simulation techniques

TL;DR: This work attempts to present a unified treatment of the various and disparate types of third generation simulators based on the concepts of large-scale decomposition theory and describes and classify simulators in terms of the role played by certain matrix forms in their formulation, namely Bordered Block Diagonal, Bordered block Triangular, and Bordered Lower Triangular.
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SAT sweeping with local observability don't-cares

TL;DR: This paper uses a novel technique to bound the use of ODCs and thus the computational effort to find them, while still finding a large fraction of them, and demonstrates that ODC-based SAT sweeping results in significantly more graph simplification with great benefit for Boolean reasoning with a moderate increase in computational effort.