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Alberto Sangiovanni-Vincentelli

Researcher at University of California, Berkeley

Publications -  946
Citations -  47259

Alberto Sangiovanni-Vincentelli is an academic researcher from University of California, Berkeley. The author has contributed to research in topics: Logic synthesis & Finite-state machine. The author has an hindex of 99, co-authored 934 publications receiving 45201 citations. Previous affiliations of Alberto Sangiovanni-Vincentelli include National University of Singapore & Lawrence Berkeley National Laboratory.

Papers
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A Formal Specification Model for Hardware/Software Codesign

TL;DR: A model for specification, partitioning, and implementation of embedded controllers for reactive real-time applications, called Codesign Finite State Machines (CFSMs), is presented, which is particularly suited to a specific class of systems with relatively low algorithmic complexity.
Book ChapterDOI

Models of computation for embedded system design

TL;DR: This paper describes in detail the CFSM model of computation, illustrating its suitability for design of reactive embedded systems and concludes with some general considerations about the use of models of computations in future design systems.
Proceedings ArticleDOI

HSIS: A BDD-Based Environment for Formal Verification

TL;DR: The essential features of HSIS, a BDD-based environment for formal verification, are described, which allows us to experiment with formal verification techniques on a variety of design problems and provides an environment for further research in formal verification.
Book ChapterDOI

Modeling and Designing Heterogeneous Systems

TL;DR: The modeling mechanism employed in Metropolis, a design environment for heterogeneous embedded systems, and a design methodology based on the mechanism experimented for wireless communication systems are presented, developed to favor the reusability of components in the systems.
Journal ArticleDOI

An embedded system for an eye-detection sensor

TL;DR: This paper presents a hardware-based embedded system for eye detection, implemented using simple logic gates, with no CPU and no addressable frame buffers, suitable for single-chip eye detection and eye-gaze tracking sensors, thus making an important step towards mass production, low cost systems.