A
Alberto Sangiovanni-Vincentelli
Researcher at University of California, Berkeley
Publications - 946
Citations - 47259
Alberto Sangiovanni-Vincentelli is an academic researcher from University of California, Berkeley. The author has contributed to research in topics: Logic synthesis & Finite-state machine. The author has an hindex of 99, co-authored 934 publications receiving 45201 citations. Previous affiliations of Alberto Sangiovanni-Vincentelli include National University of Singapore & Lawrence Berkeley National Laboratory.
Papers
More filters
Proceedings ArticleDOI
Cross-talk immune VLSI design using a network of PLAs embedded in a regular layout fabric
TL;DR: The crosstalk immunity, high speed, low area overhead and high predictability of the VLSI design methodology indicate that it is a strong candidate as the preferred design methodology in the DSM era.
Journal ArticleDOI
Optimizing the Software Architecture for Extensibility in Hard Real-Time Distributed Systems
TL;DR: A notion of extensibility metric that measures how much the execution times of tasks can be increased without violating end-to-end deadlines is adopted, followed by a mathematical programming front-end followed by postprocessing heuristics to optimize the task and message design.
Journal ArticleDOI
Delay fault coverage, test set size, and performance trade-offs
TL;DR: It is proved that 100% delay fault testability is not necessary to guarantee the speed of a combinational circuit and the test set size can be reduced while maintaining the delay fault coverage for the specified circuit speed.
Proceedings ArticleDOI
Platform-Based Design of Wireless Sensor Networks for Industrial Applications
TL;DR: This work presents a methodology, an environment and supporting tools to map an application on a wireless sensor network (WSN) and shows how the methodology covers all the aspects of the design process, from conceptual description to implementation.
Synthesis methods for field programmable gate arrays
TL;DR: The three most popular types of FPGA architectures are considered, namely those using logic blocks based on lookuptables, multiplexers and wide AND/OR arrays, and the emphasis is on tools which attempt to minimize the area of the combinational logic part of a design.