An object is to provide a semiconductor device of which a manufacturing process is not complicated and by which cost can be suppressed, by forming a thin film transistor using an oxide semiconductor film typified by zinc oxide, and a manufacturing method thereof. For the semiconductor device, a gate electrode is formed over a substrate; a gate insulating film is formed covering the gate electrode; an oxide semiconductor film is formed over the gate insulating film; and a first conductive film and a second conductive film are formed over the oxide semiconductor film. The oxide semiconductor film has at least a crystallized region in a channel region.

Semiconductor device, and manufacturing method thereof

We present a simple and usable noise model for the raw-data of digital imaging sensors This signal-dependent noise model, which gives the pointwise standard-deviation of the noise as a function of the expectation of the pixel raw-data output, is composed of a Poissonian part, modeling the photon sensing, and Gaussian part, for the remaining stationary disturbances in the output data We further explicitly take into account the clipping of the data (over- and under-exposure), faithfully reproducing the nonlinear response of the sensor We propose an algorithm for the fully automatic estimation of the model parameters given a single noisy image Experiments with synthetic images and with real raw-data from various sensors prove the practical applicability of the method and the accuracy of the proposed model

/pdf/practical-poissonian-gaussian-noise-modeling-and-fitting-for-4cn04dppj4.pdf

Practical Poissonian-Gaussian Noise Modeling and Fitting for Single-Image Raw-Data

Systems and methods for applying time-dependent algorithmic compensation functions to data output from a continuous analyte sensor. Some embodiments determine a time since sensor implantation and/or whether a newly initialized sensor has been used previously.

Systems and methods for processing analyte sensor data

Despite their increasing sophistication, wireless sensor networks still do not exploit the most powerful of the human senses: vision. Indeed, vision provides humans with unmatched capabilities to distinguish objects and identify their importance. Our work seeks to provide sensor networks with similar capabilities by exploiting emerging, cheap, low-power and small form factor CMOS imaging technology. In fact, we can go beyond the stereo capabilities of human vision, and exploit the large scale of sensor networks to provide multiple, widely different perspectives of the physical phenomena. To this end, we have developed a small camera device called Cyclops that bridges the gap between the computationally constrained wireless sensor nodes such as Motes, and CMOS imagers which, while low power and inexpensive, are nevertheless designed to mate with resource-rich hosts. Cyclops enables development of new class of vision applications that span across wireless sensor network. We describe our hardware and software architecture, its temporal and power characteristics and present some representative applications.

Cyclops: In Situ Image Sensing and Interpretation in Wireless Sensor Networks

Despite their increasing sophistication, wireless sensor networks still do not exploit the most powerful of the human senses: vision. Indeed, vision provides humans with unmatched capabilities to distinguish objects and identify their importance. Our work seeks to provide sensor networks with similar capabilities by exploiting emerging, cheap, low-power and small form factor CMOS imaging technology. In fact, we can go beyond the stereo capabilities of human vision, and exploit the large scale of sensor networks to provide multiple, widely different perspectives of the physical phenomena.To this end, we have developed a small camera device called Cyclops that bridges the gap between the computationally constrained wireless sensor nodes such as Motes, and CMOS imagers which, while low power and inexpensive, are nevertheless designed to mate with resource-rich hosts. Cyclops enables development of new class of vision applications that span across wireless sensor network. We describe our hardware and software architecture, its temporal and power characteristics and present some representative applications.

http://www.kilopixel.net/publications/sensys2005.pdf

Cyclops: in situ image sensing and interpretation in wireless sensor networks

Techniques for forming devices, such as transistors, having vertical junction edges. More specifically, shallow trenches are formed in a substrate and filled with an oxide. Cavities may be formed in the oxide and filled with a conductive material, such a heavily doped polysilicon. Vertical junctions are formed between the polysilicon and the exposed substrate at the trench edges such that during a thermal cycle, the heavily doped polysilicon will out-diffuse doping elements into the adjacent single crystal silicon advantageously forming a diode extension having desirable properties.

Transistor having vertical junction edge and method of manufacturing the same

The invention includes semiconductor packages having grooves within a semiconductor die backside; and includes semiconductor packages utilizing carbon nanostructures (such as, for example, carbon nanotubes) as thermally conductive interface materials. The invention also includes methods of cooling a semiconductor die in which coolant is forced through grooves in a backside of the die, and includes methods of making semiconductor packages.

Methods of cooling semiconductor dies

Devices and methods for providing JFET transistors with improved operating characteristics are provided. Specifically, one or more embodiments of the present invention relate to JFET transistors with a higher diode turn-on voltage. For example, one or more embodiments include a JFET with a doped silicon-carbide gate, while other embodiments include a JFET with a metal gate. One or more embodiments also relate to systems and devices in which the improved JFET may be employed, as well as methods of manufacturing the improved JFET.

JFET devices with increased barrier height and methods of making same

Some embodiments include a memory cell with two transistors and one capacitor. The transistors are a first transistor and a second transistor. The capacitor has a first node coupled with a source/drain region of the first transistor, and has a second node coupled with a source/drain region of the second transistor. The memory cell has a first body region adjacent the source/drain region of the first transistor, and has a second body region adjacent the source/drain region of the second transistor. A first body connection line couples the first body region of the memory cell to a first reference voltage. A second body connection line couples the second body region of the memory cell to a second reference voltage. The first and second reference voltages may be the same as one another, or may be different from one another.

Apparatuses having memory cells with two transistors and one capacitor, and having body regions of the transistors coupled with reference voltages

Some embodiments include an integrated structure having vertically-stacked conductive levels Upper conductive levels are memory cell levels, and a lower conductive level is a select device level Conductively-doped semiconductor material is under the select device level Channel material extends along the memory cell levels and the select device level, and extends into the conductively-doped semiconductor material A region of the channel material that extends into the conductively-doped semiconductor material is a lower region of the channel material and has a vertical sidewall Tunneling material, charge-storage material and charge-blocking material extend along the channel material and are between the channel material and the conductive levels The tunneling material, charge-storage material and charge-blocking material are not along at least a portion of the vertical sidewall of the lower region of the channel material, and the conductively-doped semiconductor material is directly against such portion Some embodiments include methods of forming integrated structures

Integrated Structures Comprising Vertical Channel Material and Having Conductively-Doped Semiconductor Material Directly Against Lower Sidewalls of the Channel Material, and Methods of Forming Integrated Structures

Chandra Mouli

Papers

Transistor having vertical junction edge and method of manufacturing the same

Methods of cooling semiconductor dies

JFET devices with increased barrier height and methods of making same

Apparatuses having memory cells with two transistors and one capacitor, and having body regions of the transistors coupled with reference voltages

Integrated Structures Comprising Vertical Channel Material and Having Conductively-Doped Semiconductor Material Directly Against Lower Sidewalls of the Channel Material, and Methods of Forming Integrated Structures