C
Chandra Mouli
Researcher at Micron Technology
Publications - 216
Citations - 3356
Chandra Mouli is an academic researcher from Micron Technology. The author has contributed to research in topics: Transistor & Field-effect transistor. The author has an hindex of 32, co-authored 216 publications receiving 3289 citations. Previous affiliations of Chandra Mouli include Aptina.
Papers
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Proceedings ArticleDOI
Derivation of threshold voltage and drain current for cylindrical MOSFET and application to a recessed MOSFET
TL;DR: In this article, the threshold voltage and drive current for a cylindrical MOSFET have been rigorously derived for the purpose of analytical calculations, and the model has been verified against TCAD simulations.
Patent
Stacked non-volatile memory with silicon carbide-based amorphous silicon finFETs
TL;DR: In this article, a stacked nonvolatile memory device using amorphous silicon based thin film transistors stacked vertically is described, where each layer is formed from a deposited a-Si channel region layer having a predetermined concentration of carbon to form a carbon rich silicon film or silicon carbide film, depending on the carbon content.
Patent
Reduced leakage dram memory cells with vertically oriented nanorods and manufacturing methods thereof
Gurtej S. Sandhu,Chandra Mouli +1 more
TL;DR: In this article, the authors describe methods and structures for reducing leakage currents in semiconductor memory storage cells, including the use of nanorods in the channel region of an access transistor.
Patent
High density memory devices having improved channel widths and cell size
TL;DR: In this paper, a memory device having decreased cell size and having transistors with increased channel widths is presented, where the top surface of the pillars are covered with gate oxide and a conductive layer to form a channel through the pillars.
Proceedings ArticleDOI
Small-Signal Analysis and Modeling of Asymmetric Source/Drain Parasitic Resistances for DRAM Access Transistors in Low-Power Applications
Young Pil Kim,Matthew Ulrich,Praveen Vaidyanathan,Venkat Ananthan,Chandra Mouli,Kunal R. Parekh +5 more
TL;DR: In this article, the small-signal conductance technique was extended to extract asymmetric source/drain parasitic resistances and applied in order to analyze the tWR delay of DRAM cell transistors in production and to develop a non-planar cell transistor such as Recessed Access Device (RAD) for low-power DRAM cells.