In the past decade, extracellular vesicles (EVs) have been recognized as potent vehicles of intercellular communication, both in prokaryotes and eukaryotes. This is due to their capacity to transfer proteins, lipids and nucleic acids, thereby influencing various physiological and pathological functions of both recipient and parent cells. While intensive investigation has targeted the role of EVs in different pathological processes, for example, in cancer and autoimmune diseases, the EV-mediated maintenance of homeostasis and the regulation of physiological functions have remained less explored. Here, we provide a comprehensive overview of the current understanding of the physiological roles of EVs, which has been written by crowd-sourcing, drawing on the unique EV expertise of academia-based scientists, clinicians and industry based in 27 European countries, the United States and Australia. This review is intended to be of relevance to both researchers already working on EV biology and to newcomers who will encounter this universal cell biological system. Therefore, here we address the molecular contents and functions of EVs in various tissues and body fluids from cell systems to organs. We also review the physiological mechanisms of EVs in bacteria, lower eukaryotes and plants to highlight the functional uniformity of this emerging communication system.

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Biological properties of extracellular vesicles and their physiological functions

Within the past decade, extracellular vesicles have emerged as important mediators of intercellular communication, being involved in the transmission of biological signals between cells in both prokaryotes and higher eukaryotes to regulate a diverse range of biological processes. In addition, pathophysiological roles for extracellular vesicles are beginning to be recognized in diseases including cancer, infectious diseases and neurodegenerative disorders, highlighting potential novel targets for therapeutic intervention. Moreover, both unmodified and engineered extracellular vesicles are likely to have applications in macromolecular drug delivery. Here, we review recent progress in understanding extracellular vesicle biology and the role of extracellular vesicles in disease, discuss emerging therapeutic opportunities and consider the associated challenges.

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Extracellular vesicles: biology and emerging therapeutic opportunities

MicroRNAs in Stress Signaling and Human Disease

The shear-responsive transcription factor Kruppel-like factor 2 (KLF2) is a critical regulator of endothelial gene expression patterns induced by atheroprotective flow. As microRNAs (miRNAs) post-transcriptionally control gene expression in many pathogenic and physiological processes, we investigated the regulation of miRNAs by KLF2 in endothelial cells. KLF2 binds to the promoter and induces a significant upregulation of the miR-143/145 cluster. Interestingly, miR-143/145 has been shown to control smooth muscle cell (SMC) phenotypes; therefore, we investigated the possibility of transport of these miRNAs between endothelial cells and SMCs. Indeed, extracellular vesicles secreted by KLF2-transduced or shear-stress-stimulated HUVECs are enriched in miR-143/145 and control target gene expression in co-cultured SMCs. Extracellular vesicles derived from KLF2-expressing endothelial cells also reduced atherosclerotic lesion formation in the aorta of ApoE(-/-) mice. Combined, our results show that atheroprotective stimuli induce communication between endothelial cells and SMCs through an miRNA- and extracellular-vesicle-mediated mechanism and that this may comprise a promising strategy to combat atherosclerosis.

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Atheroprotective communication between endothelial cells and smooth muscle cells through miRNAs.

State-of-the-art on use of insects as animal feed.

The Functional Failure Rate analysis of today’s complex circuits is a difficult task and requires a significant investment in terms of human efforts, processing resources and tool licenses. Thereby, de-rating or vulnerability factors are a major instrument of failure analysis efforts. Usually computationally intensive fault-injection simulation campaigns are required to obtain a fine-grained reliability metrics for the functional level. Therefore, the use of machine learning algorithms to assist this procedure and thus, optimising and enhancing fault injection efforts, is investigated in this paper. Specifically, machine learning models are used to predict accurate per-instance Functional De-Rating data for the full list of circuit instances, an objective that is difficult to reach using classical methods. The described methodology uses a set of per-instance features, extracted through an analysis approach, combining static elements (cell properties, circuit structure, synthesis attributes) and dynamic elements (signal activity). Reference data is obtained through first-principles fault simulation approaches. One part of this reference dataset is used to train the machine learning model and the remaining is used to validate and benchmark the accuracy of the trained tool. The presented methodology is applied on a practical example and various machine learning models are evaluated and compared.

Machine Learning to Tackle the Challenges of Transient and Soft Errors in Complex Circuits

Nowadays Xilinx Tools trend is to increase design abstraction level. This allows users to create complex FPGA-based projects and designs without the needs of in-depth knowledge of low level resources implementation and configuration memory usage. The design automation has the advantage to make the development process more rapid and affordable for a larger range of users. On the other hand, this trend has the drawback of the lack of accessibility to low level information, above all on FPGA fabric and configuration memory. This is crucial in research, especially the one oriented to the development of specific mission critical applications. In the aerospace fields an in-depth knowledge of the device is fundamental to guarantee high performances and high dependability to the application. In this paper we propose COMET: an interface at the lowest level to enable the study of SRAM-based FPGA's configuration memory, allowing the visualization, the analysis and the manipulation of its content. This tool allows bitstream decryption and, bitstream fine-grained modification as consequence. These features provide efficient means to perform detailed fault injection and simulation or to cleverly perform Partial Dynamic Reconfiguration, increasing dependability and performances of FPGA-based aerospace mission critical applications.

COMET: a Configuration Memory Tool to Analyze, Visualize and Manipulate FPGAs Bitstream

Hardware fault emulation for Application Specific Integrated Circuits (ASICs) on FPGAs can considerably reduce the time required for the fault simulation. This paper presents a methodology to emulate ASIC faults on state-of-the-art FPGAs. The fault emulation is achieved by following a fully automated process consisting of: constrained technology mapping of ASIC net-list; creation of fault dictionary, generation of faulty partial bit-streams and fault emulation. The proposed approach exploits run-time partial reconfiguration techniques for fault injection and avoids full net-list re-compilations. The method's feasibility is assessed through carefully selected circuits and overhead in terms of area and timing is reported.

Effective emulation of permanent faults in ASICs through dynamically reconfigurable FPGAs

General Purpose Graphic Processing Units (GPGPUs) are effective solutions for high-demand data applications which involve multi-signal, image and video processing thanks to their powerful parallel architecture. In the last years, GPGPUs have been considered also for safety-critical applications, such as autonomous and semi-autonomous car driving systems. New GPGPU devices include an increasing number of parallel cores in order to increase throughput and performance. This increment in the number of cores and the requirements in terms of power consumption force designers to use aggressive semiconductor technologies. Nevertheless, those new devices can be seriously affected by radiation effects, modeled as Single Event Upsets (SEUs). SEUs could generate unexpected operation effects in the applications which could be unacceptable for the safety-critical ones. This work analyzes the SEU effects resorting to an open-source model of a GPGPU based on the Nvidia’s G80 architecture and aims at complementing previous analysis based on radiation experiments.

On the evaluation of SEU effects in GPGPUs

Reconfigurable devices are widely attractive for several application fields thanks to their size, rapid prototyping characteristics, flexibility and upgradability. Thanks to partial Reconfiguration features, FPGA becomes the golden core of the adaptive computation paradigm since they may dynamically change their functionalities based on the elaboration request. Today, adaptive computation is mainly controlled at a coarse-grain granularity while no solutions exist to act at the fine granularity level especially to reprogram the FPGA routing interconnection. The purpose of this work is to propose an embedded core able to reconfigure the routing resources without the usage of external computational units. The developed core implements a Path Finding-based algorithm able to perform the full routability of complex designs. The core has been devised minimizing the area overhead and the requested computational power by wisely selecting a suitable subset of wiring segments. The functionalities of the core have been tested on a Xilinx SRAM-based FPGAs Zynq device using three different circuit benchmarks. Experimental results demonstrated that the core is able to successfully re-route almost 95% of the selected nets without introducing a relevant delay or area overhead.

Luca Sterpone

Papers

Machine Learning to Tackle the Challenges of Transient and Soft Errors in Complex Circuits

COMET: a Configuration Memory Tool to Analyze, Visualize and Manipulate FPGAs Bitstream

Effective emulation of permanent faults in ASICs through dynamically reconfigurable FPGAs

On the evaluation of SEU effects in GPGPUs

Self rerouting of dynamically reconfigurable SRAM-based FPGAs