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Luca Sterpone

Researcher at Polytechnic University of Turin

Publications -  236
Citations -  3523

Luca Sterpone is an academic researcher from Polytechnic University of Turin. The author has contributed to research in topics: Fault injection & Field-programmable gate array. The author has an hindex of 24, co-authored 222 publications receiving 3125 citations. Previous affiliations of Luca Sterpone include Instituto Politécnico Nacional.

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Proceedings ArticleDOI

A new placement algorithm for the optimization of fault tolerant circuits on reconfigurable devices

TL;DR: An innovative placement algorithm able to implement fault tolerant circuits on SRAM-based FPGAs while reducing the performance penalties is presented, based on a model-based topology heuristic that address the arithmetic modules implemented on the FPGA reducing the interconnection delays between their resources.
Book ChapterDOI

Analysis and Clustering of MicroRNA Array: A New Efficient and Reliable Computational Method

TL;DR: The support of systems and tools that allow an efficient and more robust analysis of miRNA’s expression levels become increasing mandatory to have a better disease identification.
Proceedings ArticleDOI

On the mitigation of single event transients on flash-based FPGAs

TL;DR: A new workflow to evaluate SET phenomena in a specific convergence case and introduce a new mitigation of SET pulse without introducing any performance penalization to the original netlist is developed.
Book ChapterDOI

On the Automatic Generation of Software-Based Self-Test Programs for Functional Test and Diagnosis of VLIW Processors

TL;DR: In this paper, the authors present a new method that, starting from previously known algorithms, automatically generates an effective test program able to still reach high fault coverage on the VLIW processor under test, while minimizing the test duration and the test code size.
Proceedings ArticleDOI

SETA: A CAD Tool for Single Event Transient Analysis and Mitigation on Flash-Based FPGAs

TL;DR: A new CAD tool has been developed in order to evaluate the sensitivity of the implemented circuit regarding SET and to mitigate their effects and the experimental results demonstrated the feasibility and efficiency of proposed tool.