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Luca Sterpone

Researcher at Polytechnic University of Turin

Publications -  236
Citations -  3523

Luca Sterpone is an academic researcher from Polytechnic University of Turin. The author has contributed to research in topics: Fault injection & Field-programmable gate array. The author has an hindex of 24, co-authored 222 publications receiving 3125 citations. Previous affiliations of Luca Sterpone include Instituto Politécnico Nacional.

Papers
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Proceedings ArticleDOI

A Novel Error Rate Estimation Approach forUltraScale+ SRAM-based FPGAs

TL;DR: A new estimation approach able to consider the radiation effects on the configuration memory and logic layer of FPGAs, providing a comprehensive Application Error Rate probability estimation is proposed.
Proceedings ArticleDOI

Test, Reliability and Functional Safety Trends for Automotive System-on-Chip

TL;DR: In this article , three contributions by industry professionals and university researchers describe different trends in automotive products, including both manufacturing test and run-time reliability strategies, from optimizing the final test before shipment to market to in-field reliability during operative life.
Proceedings ArticleDOI

Differential gene expression graphs: A data structure for classification in DNA microarrays

TL;DR: An innovative data structure to be used as a backbone in designing microarray phenotype sample classifiers that shows a number of properties that are perfectly suited to address several problems like feature extraction, clustering, and classification.
Proceedings ArticleDOI

On the Estimation of Complex Circuits Functional Failure Rate by Machine Learning Techniques

TL;DR: A new approach is proposed which uses Machine Learning to estimate the Functional De-Rating of individual flip-flops and thus, optimising and enhancing fault injection efforts.
Proceedings ArticleDOI

Robustness analysis of soft error accumulation in SRAM-FPGAs using FLIPPER and STAR/RoRA

TL;DR: A methodology for analyzing the robustness of circuits implemented by SRAM-based FPGAs against the accumulation of soft errors within the configuration memory is described.