In the past decade, extracellular vesicles (EVs) have been recognized as potent vehicles of intercellular communication, both in prokaryotes and eukaryotes. This is due to their capacity to transfer proteins, lipids and nucleic acids, thereby influencing various physiological and pathological functions of both recipient and parent cells. While intensive investigation has targeted the role of EVs in different pathological processes, for example, in cancer and autoimmune diseases, the EV-mediated maintenance of homeostasis and the regulation of physiological functions have remained less explored. Here, we provide a comprehensive overview of the current understanding of the physiological roles of EVs, which has been written by crowd-sourcing, drawing on the unique EV expertise of academia-based scientists, clinicians and industry based in 27 European countries, the United States and Australia. This review is intended to be of relevance to both researchers already working on EV biology and to newcomers who will encounter this universal cell biological system. Therefore, here we address the molecular contents and functions of EVs in various tissues and body fluids from cell systems to organs. We also review the physiological mechanisms of EVs in bacteria, lower eukaryotes and plants to highlight the functional uniformity of this emerging communication system.

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Biological properties of extracellular vesicles and their physiological functions

Within the past decade, extracellular vesicles have emerged as important mediators of intercellular communication, being involved in the transmission of biological signals between cells in both prokaryotes and higher eukaryotes to regulate a diverse range of biological processes. In addition, pathophysiological roles for extracellular vesicles are beginning to be recognized in diseases including cancer, infectious diseases and neurodegenerative disorders, highlighting potential novel targets for therapeutic intervention. Moreover, both unmodified and engineered extracellular vesicles are likely to have applications in macromolecular drug delivery. Here, we review recent progress in understanding extracellular vesicle biology and the role of extracellular vesicles in disease, discuss emerging therapeutic opportunities and consider the associated challenges.

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Extracellular vesicles: biology and emerging therapeutic opportunities

MicroRNAs in Stress Signaling and Human Disease

The shear-responsive transcription factor Kruppel-like factor 2 (KLF2) is a critical regulator of endothelial gene expression patterns induced by atheroprotective flow. As microRNAs (miRNAs) post-transcriptionally control gene expression in many pathogenic and physiological processes, we investigated the regulation of miRNAs by KLF2 in endothelial cells. KLF2 binds to the promoter and induces a significant upregulation of the miR-143/145 cluster. Interestingly, miR-143/145 has been shown to control smooth muscle cell (SMC) phenotypes; therefore, we investigated the possibility of transport of these miRNAs between endothelial cells and SMCs. Indeed, extracellular vesicles secreted by KLF2-transduced or shear-stress-stimulated HUVECs are enriched in miR-143/145 and control target gene expression in co-cultured SMCs. Extracellular vesicles derived from KLF2-expressing endothelial cells also reduced atherosclerotic lesion formation in the aorta of ApoE(-/-) mice. Combined, our results show that atheroprotective stimuli induce communication between endothelial cells and SMCs through an miRNA- and extracellular-vesicle-mediated mechanism and that this may comprise a promising strategy to combat atherosclerosis.

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Atheroprotective communication between endothelial cells and smooth muscle cells through miRNAs.

State-of-the-art on use of insects as animal feed.

SRAM-Based FPGAs represent a low-cost alternative to ASIC device thanks to their high performance and design flexibility. In particular, for aerospace and avionics application fields, SRAM-based FPGAs are increasingly adopted for their configurability features making them a viable solution for long-time applications. However, these fields are characterized by a radiation environment that makes the technology extremely sensitive to radiation-induced Single Event Upsets (SEUs) in the SRAM-based FPGA's configuration memory. Configuration scrubbing and Triple Modular Redundancy (TMR) have been widely adopted in order to cope with SEU effects. However, modern FPGA devices are characterized by a heterogeneous routing resource distribution and a complex configuration memory mapping causing an increasing sensitivity to Cross Domain Errors affecting the TMR structure. In this paper we developed a new methodology to calculate the reliability of TMR architecture considering the intrinsic characteristics of the new generation of SRAM-based FPGAs. The method includes the analysis of the configuration bit sharing phenomena and of the routing long lines. We experimentally evaluate the method of various benchmark circuits evaluating the Mean Upset To Failure (MUTF). Finally, we used the results of the developed method to implement an improved design achieving 29x improvement of the MUTF.

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Analysis of radiation-induced cross domain errors in TMR architectures on SRAM-based FPGAs

On the analysis of radiation-induced Single Event Transients on SRAM-based FPGAs

In the recent years both software and hardware techniques have been adopted to carry out reliable designs, aimed at autonomously detecting the occurrence of faults, to allow discarding erroneous data and possibly performing the recovery of the system. The aim of this paper is the introduction of a combined use of software and hardware approaches to achieve a complete fault coverage in generic IP processors, with respect to SEU faults. Software techniques are preferably adopted to reduce the necessity and costs of modifying the processor architecture; since a complete fault coverage cannot be achieved, partial hardware redundancy techniques are then introduced to deal with the remaining, not covered, faults. The paper presents the methodological approach adopted to achieve the complete fault coverage, the proposed resulting architecture, and the experimental results gathered from the fault injection analysis campaign.

Combined software and hardware techniques for the design of reliable IP processors

Modern neural network complexity has grown dramatically in recent years, leading to the adoption of hardware-accelerated solutions to cope with the computational power required by the new network architectures. The possibility to adapt the network size and performance to different platforms enhanced the interests of safety-critical applications such as automotive and avionic. Today, the reliability evaluation of neural networks is still premature and requires platforms to measure the safety standards required by mission-critical applications. For this reason, the interest in studying the reliability of neural networks is growing. In this work, we propose a new approach for evaluating the resiliency of neural networks by using programmable hardware of hybrid platforms. The approach relies on the reconfigurable hardware for emulating the target hardware platform and performing the fault injection process. The main advantage of the proposed approach is to involve the on-hardware execution of the neural network in the reliability analysis without modifying the hardware implementation of the network under analysis, and addressing specific fault models. The implementation of FireNN, the platform based on the proposed approach is detailly described in the paper. Experimental analyses are performed using fault injection on the AlexNet Convolutional Neural Network. The analyses are carried out by means of the FireNN platform and the obtained results are compared with the outcome of traditional software-level evaluations. Results are commented taking into account the insight into the hardware level achieved by using the FireNN platform.

FireNN: Neural Networks Reliability Evaluation on Hybrid Platforms

Electronic systems for safety critical applications such as space and avionics need the maximum level of dependability for guarantee the success of their missions. Simultaneously the computation capabilities required in these fields are constantly increasing for afford the implementation of different kind of applications ranging from signal processing to networking. SRAM-based FPGAs are the candidate devices to achieve this goal thanks to their high versatility of implementing complex circuits with a very short development time. However, in critical environments, the presence of Single Event Upsets (SEUs) affecting the FPGA’s functionalities, requires the adoption of specific fault tolerant techniques, like Triple Modular Redundancy (TMR), able to increase the protection capability against radiation effects, but on the other side, introducing a dramatic penalty in terms of performances. In this paper, it is proposed a new timing-driven placement algorithm for implementing soft-errors resilient circuits on SRAM-based FPGAs with a negligible degradation of performance. The algorithm is based on a placement heuristic able to remove the crossing error domains while decreasing the routing congestions and delay inserted by the TMR routing and voting scheme. Experimental analysis performed by timing analysis and SEU static analysis point out a performance improvement of 29p on the average with respect to standard TMR approach and an increased robustness against SEU affecting the FPGA’s configuration memory. Accurate analyses of SEUs sensitivity and performance optimization have been performed on a real microprocessor core demonstrating an improvement of performances of more than 62p.

Luca Sterpone

Papers

Analysis of radiation-induced cross domain errors in TMR architectures on SRAM-based FPGAs

On the analysis of radiation-induced Single Event Transients on SRAM-based FPGAs

Combined software and hardware techniques for the design of reliable IP processors

FireNN: Neural Networks Reliability Evaluation on Hybrid Platforms

A New Timing Driven Placement Algorithm for Dependable Circuits on SRAM-based FPGAs