L
Luca Sterpone
Researcher at Polytechnic University of Turin
Publications - 236
Citations - 3523
Luca Sterpone is an academic researcher from Polytechnic University of Turin. The author has contributed to research in topics: Fault injection & Field-programmable gate array. The author has an hindex of 24, co-authored 222 publications receiving 3125 citations. Previous affiliations of Luca Sterpone include Instituto Politécnico Nacional.
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Proceedings ArticleDOI
A Low-Cost Emulation System for Fast Co-verification and Debug
J. Lagos-Benites,Michelangelo Grosso,Luca Sterpone,M. Sonza Reorda,G. Audisio,M. Pipponzi,M. Sabatini +6 more
TL;DR: A flexible system for SoC co-verification is proposed, built around an Infrastructure Microprocessor (IM), providing improved controllability and observability in a fast self-contained FPGA-based emulation environment.
Reference EntryDOI
FPGA PAL Design Tools
TL;DR: A survey of the CAD tools for the programmable devices design phases is presented exploring the variety and particularity offered and analyzing the most influcnt results achieved on this area.
Proceedings ArticleDOI
Gene expression reliability estimation through cluster-based analysis
TL;DR: A new method for estimate the quality degree and the data's reliability of a microarray analysis is presented and the efficiency of the proposed approach in terms of genes expression classification has been demonstrated through a clustering supervised analysis performed on a set of three different histological samples related to the Lymphoma's cancer disease.
Proceedings ArticleDOI
A Placement-Oriented Mitigation Technique for Single Event Effect in Monolithic 3D IC
TL;DR: A new placement technique that takes advantage of the multi-tiers feature of 3D technology to increase the reliability of3D designs and reduces the radiation-induced error sensitivity of circuits.
Proceedings ArticleDOI
IbIS: Interface-based Interconnection Structure for Dynamically Reconfigurable FPGAs
Ludovica Bozzoli,Luca Sterpone +1 more
TL;DR: An Interface-based communication architecture is proposed, which simplify the interaction mechanism and the DRPM architecture, reducing both delay and resources overhead with respect to the state-of-the-art solutions.