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Luca Sterpone
Researcher at Polytechnic University of Turin
Publications - 236
Citations - 3523
Luca Sterpone is an academic researcher from Polytechnic University of Turin. The author has contributed to research in topics: Fault injection & Field-programmable gate array. The author has an hindex of 24, co-authored 222 publications receiving 3125 citations. Previous affiliations of Luca Sterpone include Instituto Politécnico Nacional.
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An Analysis Based on Fault Injection of Hardening Techniques for SRAM-Based FPGAs
TL;DR: This work analyzed by means of extensive fault-injection experiments the TMR architecture and identified some of the causes that are responsible for the escaped faults, and proposed possible solutions.
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Coping With the Obsolescence of Safety- or Mission-Critical Embedded Systems Using FPGAs
TL;DR: A design flow is presented, describing its applicability to the implementation of processor cores, to be employed as a replacement of obsolete parts in safety- or mission-critical applications and there is a strong dependence of the reliability of the design with the specific application.
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Experimental Validation of a Tool for Predicting the Effects of Soft Errors in SRAM-Based FPGAs
TL;DR: An analytical method to predict SEE effects based on the analysis of the circuit the FPGA implements, which does not require either simulation or fault injection is provided, by comparing the results it provides with those coming from accelerated testing.
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An Analytical Model of the Propagation Induced Pulse Broadening (PIPB) Effects on Single Event Transient in Flash-Based FPGAs
TL;DR: Experimental results matched the electrical simulations, which validate the effectiveness of the method, and electrical-based fault injection was performed on the FPGA board and at the electrical model.
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Analysis of SET Propagation in Flash-Based FPGAs by Means of Electrical Pulse Injection
TL;DR: A technique based on electrical pulse injection for the analysis of SETs propagation within logic resources of Flash-based FPGAs is developed, providing detailed characterization of basic gates and realistic routing and logic paths.