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Oreste Villa

Researcher at Nvidia

Publications -  81
Citations -  2693

Oreste Villa is an academic researcher from Nvidia. The author has contributed to research in topics: Multithreading & Shared memory. The author has an hindex of 28, co-authored 79 publications receiving 2054 citations. Previous affiliations of Oreste Villa include Environmental Molecular Sciences Laboratory & University of California, Los Angeles.

Papers
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Journal ArticleDOI

NWChem: Past, present, and future

Edoardo Aprà, +113 more
TL;DR: The NWChem computational chemistry suite is reviewed, including its history, design principles, parallel tools, current capabilities, outreach, and outlook.
Journal ArticleDOI

NWChem: Past, Present, and Future

Edoardo Aprà, +113 more
TL;DR: The NWChem computational chemistry suite as discussed by the authors provides tools to support and guide experimental efforts and for the prediction of atomistic and electronic properties by using first-principledriven methodologies to model complex chemical and materials processes.
Proceedings ArticleDOI

MCM-GPU: Multi-Chip-Module GPUs for Continued Performance Scalability

TL;DR: It is demonstrated that package-level integration of multiple GPU modules to build larger logical GPUs can enable continuous performance scaling beyond Moore's law and solve the need for higher performing GPUs in many domains.
Proceedings ArticleDOI

Dynamic load balancing on single- and multi-GPU systems

TL;DR: Experimental results show that the proposed task-based dynamic load-balancing solution can utilize the hardware more efficiently than the CUDA scheduler for unbalanced workload, and achieves near-linear speedup, load balance, and significant performance improvement over techniques based on standard CUDA APIs.
Proceedings ArticleDOI

Scaling the power wall: a path to exascale

TL;DR: This paper evaluates several architectural concepts for a set of HPC applications demonstrating expected energy efficiency improvements resulting from circuit and packaging innovations such as low-voltage SRAM, low-energy signalling, and on-package memory and discusses the scaling of these features with respect to future process technologies.