Showing papers by "Peide D. Ye published in 2021"

Why In2O3 Can Make 0.7 nm Atomic Layer Thin Transistors.

Abstract: In this work, we demonstrate enhancement-mode field-effect transistors by an atomic-layer-deposited (ALD) amorphous In2O3 channel with thickness down to 0.7 nm. Thickness is found to be critical on the materials and electron transport of In2O3. Controllable thickness of In2O3 at atomic scale enables the design of sufficient 2D carrier density in the In2O3 channel integrated with the conventional dielectric. The threshold voltage and channel carrier density are found to be considerably tuned by channel thickness. Such a phenomenon is understood by the trap neutral level (TNL) model, where the Fermi-level tends to align deeply inside the conduction band of In2O3 and can be modulated to the bandgap in atomic layer thin In2O3 due to the quantum confinement effect, which is confirmed by density function theory (DFT) calculation. The demonstration of enhancement-mode amorphous In2O3 transistors suggests In2O3 is a competitive channel material for back-end-of-line (BEOL) compatible transistors and monolithic 3D integration applications.

Scaled Atomic-Layer-Deposited Indium Oxide Nanometer Transistors With Maximum Drain Current Exceeding 2 A/mm at Drain Voltage of 0.7 V

Abstract: In this work, we demonstrate scaled back-end-of-line (BEOL) compatible indium oxide (In2O3) transistors by atomic layer deposition (ALD) with channel thickness (Tch) of 1.0-1.5 nm, channel length (Lch) down to 40 nm, and equivalent oxide thickness (EOT) of 2.1 nm, with record high drain current of 2.0 A/mm at VDS of 0.7 V among all oxide semiconductors. Enhancement-mode In2O3 transistors with ID over 1.0 A/mm at VDS of 1 V are also achieved by controlling the channel thickness down to 1.0 nm at atomic layer scale. Such high current density in a relatively low mobility amorphous oxide semiconductor is understood by the formation of high density 2D channel beyond $4\times 10^{13}$ /cm2 at HfO2/In2O3 oxide/oxide interface.

Enhancement-Mode Atomic-Layer-Deposited In 2 O 3 Transistors With Maximum Drain Current of 2.2 A/mm at Drain Voltage of 0.7 V by Low-Temperature Annealing and Stability in Hydrogen Environment

Abstract: In this article, we demonstrate atomic-layer-deposited (ALD) indium oxide (In2O3) transistors with a record high drain current of 2.2 A/mm at ${V}_{DS}$ of 0.7 V among oxide semiconductor transistors with the enhancement-mode operation. The impact of back-end-of-line (BEOL) compatible low-temperature annealing is systematically studied on these highly scaled In2O3 transistors with channel length ( ${L}_{ch}$ ) down to 40 nm, channel thickness ( ${T}_{ch}$ ) down to 1.2 nm, and equivalent oxide thickness (EOTs) of 2.1 nm, at annealing temperatures from 250 °C to 350 °C in N2, O2, and forming gas (FG, 96% N2/4% H2) environments. Annealing in all different environments is found to significantly improve the performance of ALD In2O3 transistors, resulting in enhancement-mode operation, high mobility, reduced bulk and interface trap density ( $\text{D}_{it}$ as low as $6.3\times 10^{11}$ cm $^{-2}\cdot $ eV−1), and nearly ideal subthreshold slope (SS) of 63.8 mV/dec. Remarkably, the ALD In2O3 devices are found to be stable in hydrogen environment, being less affected by the well-known hydrogen doping issue in indium–gallium–tin-oxide (IGZO). Therefore, low-temperature ALD In2O3 transistors are highly compatible with the hydrogen-rich environment in BEOL fabrication processes.

Enhancement-mode atomic-layer thin In2O3 transistors with maximum current exceeding 2 A/mm at drain voltage of 0.7 V enabled by oxygen plasma treatment

Abstract: In this Letter, enhancement-mode operation in devices with 1.5 nm atomic-layer thin In2O3 channels over a wide range of channel lengths down to 40 nm is demonstrated using an O2 plasma treatment at room temperature. Drain currents (ID) in excess of 2 A/mm at a drain-to-source bias (VDS) of 0.7 V are achieved in enhancement mode with significantly improved subthreshold swing down to near-ideal 65 mV/dec, suggesting that O2 plasma treatment is very effective at reducing bulk and interface defects. By using low-temperature O2 plasma, the fabrication process remains back-end-of-line compatible while enabling a clear route toward high-performance In2O3 transistors and circuitry.

Asymmetric Metal/α-In2Se3/Si Crossbar Ferroelectric Semiconductor Junction.

Abstract: A ferroelectric semiconductor junction is a promising two-terminal ferroelectric device for nonvolatile memory and neuromorphic computing applications. In this work, we propose and report the experimental demonstration of asymmetric metal/α-In2Se3/Si crossbar ferroelectric semiconductor junctions (c-FSJs). The depletion in doped Si is used to enhance the modulation of the effective Schottky barrier height through the ferroelectric polarization. A high-performance α-In2Se3 c-FSJ is achieved with a high on/off ratio > 104 at room temperature, on/off ratio > 103 at an elevated temperature of 140 °C, retention > 104 s, and endurance > 106 cycles. The on/off ratio of the α-In2Se3 asymmetric FSJs can be further enhanced to >108 by introducing a metal/α-In2Se3/insulator/metal structure.

High-Performance Atomic-Layer-Deposited Indium Oxide 3-D Transistors and Integrated Circuits for Monolithic 3-D Integration

Abstract: In this work, we report the experimental demonstration of In₂O₃ 3 D transistors coated on fin structures and integrated circuits by a back end of line BEOL compatible atomic layer deposition ALD process High performance planar back gate In₂O₃ transistors with high mobility of 113 cm² V·s and high maximum drain current ( $I_{{D}}$ ) of 2.5 mA/μm are achieved by channel thickness engineering and postdeposition annealing. The high-performance ALD In₂O₃-based zero- $V_{{GS}}$ -load inverter is demonstrated with a maximum voltage gain of 38 V/V and a minimum supply voltage ( $V_{{DD}}$ ) down to 0.5 V. Top-gate indium oxide (In₂O₃) transistors by low-temperature ALD of both gate insulator and channel semiconductor are also demonstrated with $I_{{D}}$ of 570 μA/μm and low subthreshold slope (SS) down to 84.6 mV/decade. ALD In₂O₃ 3-D Fin transistors with the top-gate structure are then demonstrated, benefiting from the conformal deposition capability of ALD. These results suggest that ALD oxide semiconductors and devices have unique advantages and are promising toward BEOL-compatible monolithic 3-D integration for 3-D integrated circuits.

BEOL Compatible Indium-Tin-Oxide Transistors: Switching of Ultrahigh-Density 2-D Electron Gas Over 0.8 × 10 14 /cm 2 at Oxide/Oxide Interface by the Change of Ferroelectric Polarization

Abstract: In this work, we report back-end-of-line (BEOL) compatible indium-tin-oxide (ITO) transistors with ferroelectric (FE) Hf0.5Zr0.5O2 (HZO) as gate insulator. A tunable high-density 2-D electron gas over 0.8 $\sf \times \,\,10^{14}$ /cm2 is achieved at the HZO/ITO oxide/oxide interface because of the FE polarization, which is confirmed by ${I}$ – ${V}$ , positive up and negative down (PUND), and Hall measurements. Such high carrier density can be completely modulated and switched on and off by FE polarization switching, enabling high mobility ITO transistor with high ON-current and high ON/OFF ratio.

First Demonstration of Atomic-Layer-Deposited BEOL-Compatible In 2 O 3 3D Fin Transistors and Integrated Circuits: High Mobility of 113 cm 2 /V•s, Maximum Drain Current of 2.5 mA/μm and Maximum Voltage Gain of 38 V/V in In 2 O 3 Inverter

Abstract: In this work, we report the first demonstration of In 2 O 3 3D transistors coated on fin-structures and integrated circuits by a back-end-of-line (BEOL) compatible atomic layer deposition (ALD) process. High performance planar In 2 O 3 transistors with high mobility of 113 cm2/V • s and record high maximum drain current of 2.5 mA/μm are achieved by channel thickness engineering and post-deposition annealing. High-performance ALD In 2 O 3 based zero-V GS -load inverter is demonstrated with maximum voltage gain of 38 V/V and minimum supply voltage (V DD ) down to 0.5 V. ALD In 2 O 3 3D Fin transistors are also demonstrated, benefiting from the conformal deposition capability of ALD. These results suggest ALD oxide semiconductors and devices have unique advantages and are promising toward BEOL-compatible monolithic 3D integration for 3D integrated circuits.

Quantitative Characterization of Ferroelectric/Dielectric Interface Traps by Pulse Measurements

Abstract: The ferroelectric (FE) polarization switching behavior in the HfZrO2 (HZO) FE/dielectric (FE/DE) stack is investigated systematically by charge responses from pulse measurements The trapped charge density at the FE/DE interface related with the FE polarization switching is found to be $12\,\times \,10^{14}$ cm−2 according to the leakage-current-assist polarization switching mechanism Furthermore, by the time-dependent nonswitching charge responses, the extra FE/DE interface trap density of $11\,\times \,10^{13}$ cm−2 is confirmed, which is not related but can be detected along with the FE polarization switching The quantitative characterization reveals the huge amount of FE/DE interface traps and their dominant role in the FE operation of HZO FE/DE stack, which improves the proposed leakage-current-assist polarization switching model This improved model provides a more comprehensive understanding of the polarization switching in the HZO FE/DE stack and new insights on HZO negative-capacitance (NC) and FE field-effect transistors (FETs)

First Experimental Demonstration of Robust HZO/β-Ga₂O₃ Ferroelectric Field-Effect Transistors as Synaptic Devices for Artificial Intelligence Applications in a High-Temperature Environment

Abstract: We have experimentally demonstrated robust beta-gallium oxide ( $\beta $ -Ga2O3) ferroelectric (FE) field-effect transistors (FeFETs) on a sapphire substrate operated up to 400 °C. Atomic layer deposited (ALD) Hf0.5 Zr0.5O2 [hafnium zirconium oxide (HZO)] is used as the FE dielectric. The HZO/ $\beta $ -Ga2O3 FeFETs are studied for their synaptic behavior applications at elevated temperatures. The devices show distinguishable polarization switching operation with the output conductance quasi-linearly controlled by the number of input pulses on the FE gate. In a simulation, on-chip learning accuracy reaches 94% at elevated temperatures using the Modified National Institute of Standards and Technology (MNIST) data set with a simple two-layer multilayer perceptron (MLP) network. These ultra wide bandgap semiconductor devices have the potential to fill the need for harsh environment neuromorphic applications.

Multi-domain Polarization Switching in Hf0.5Zr0.5O2-Dielectric Stack: The Role of Dielectric Thickness.

Abstract: We investigate the polarization switching mechanism in ferroelectric-dielectric (FE-DE) stacks and its dependence on the dielectric thickness (TDE). We fabricate HZO-Al2O3 (FE-DE) stack and experimentally demonstrate a decrease in remnant polarization and an increase in coercive voltage of the FE-DE stack with an increase in TDE. Using phase-field simulations, we show that an increase in TDE results in a larger number of reverse domains in the FE layer to suppress the depolarization field, which leads to a decrease in remanent polarization and an increase in coercive voltage. Further, the applied voltage-driven polarization switching suggests domain-nucleation dominant characteristics for low TDE, and domain-wall motion-induced behavior for higher TDE. In addition, we show that the hysteretic charge-voltage characteristics of the FE layer in the FE-DE stack exhibit a negative slope region due to the multi-domain polarization switching in the FE layer. Based on our analysis, the trends in charge-voltage characteristics of the FE-DE stack with respect to different TDE (which are out of the scope of single-domain models) can be described well with multi-domain polarization switching mechanisms.

The Critical Role of Charge Balance on the Memory Characteristics of Ferroelectric Field-Effect Transistors

Abstract: Ferroelectric field-effect transistors (Fe-FETs) with ferroelectric hafnium oxide (FE HfO2) as gate insulator are being extensively explored as a promising device candidate for three-dimensional (3D) NAND memory application. FE HfO2 exhibits long retention over 10 years, high endurance over 1012 cycles, high speed with sub-ns polarization switching, and high remnant polarization of 10-30 {\mu}C/cm2. However, the performance of Fe-FETs is known to be much worse than FE HfO2 capacitors, which is not completely understood. In this work, we developed a comprehensive Fe-FET model based on a charge balance framework. The role of charge balance and the impact of leakage-assist-switching mechanism on the memory characteristics of Fe-FETs with M/FE/DE/S (Metal/Ferroelectric/Dielectric/Semiconductor) gate stack is studied. It is found that the FE/DE interface and DE layer instead of FE layer is critical to determine the memory characteristics of Fe-FETs, and experimental Fe-FETs can be well explained by this model, where the discrepancy between FE capacitors and Fe-FETs are successfully understood.

Mechanical Anisotropy in Two-Dimensional Selenium Atomic Layers

Abstract: Two-dimensional (2D) trigonal selenium (t-Se) has become a new member in 2D semiconducting nanomaterial families. It is composed of well-aligned one-dimensional Se atomic chains bonded via van der Waals (vdW) interaction. The contribution of this unique anisotropic nanostructure to its mechanical properties has not been explored. Here, for the first time, we combine experimental and theoretical analyses to study the anisotropic mechanical properties of individual 2D t-Se nanosheets. It was found that its fracture strength and Young's modulus parallel to the atomic chain direction are much higher than along the transverse direction, which was attributed to the weak vdW interaction between Se atomic chains as compared to the covalent bonding within individual chains. Additionally, two distinctive fracture modes along two orthogonal loading directions were identified. This work provides important insights into the understanding of anisotropic mechanical behaviors of 2D semiconducting t-Se and opens new possibilities for future applications.

Polarization switching in Hf0.5Zr0.5O2-dielectric stack: The role of dielectric layer thickness

Abstract: Understanding the role of the dielectric (DE) layer in ferroelectric (FE) Hf0.5Zr0.5O2 (HZO) based devices (e.g., ferroelectric-field-effect-transistors, FE-FETs) is important to enable their application-driven optimizations. To that end, in this work, we systematically investigate the polarization switching mechanisms in FE–DE stacks and analyze their dependence on the dielectric layer thickness (TDE). First, we fabricate a HZO–Al2O3 (FE–DE) stack and experimentally demonstrate a decrease in remanent polarization and an increase in coercive voltage with an increase in TDE. As such dependencies are out of the scope of commonly used single domain polarization switching models, therefore, we argue that the consideration of the multi-domain model is essential for analyzing the polarization switching in HZO. Then, using phase-field simulations of the FE–DE stack, we show that an increase in TDE results in a larger number of reverse domains in the FE layer to suppress the depolarization field, which leads to a decrease in the remanent polarization and an increase in the coercive voltage. Furthermore, our analysis signifies that the polarization switching mechanism in HZO can be modulated from domain-nucleation based to domain-wall motion based by increasing the TDE and that can serve as a potential knob for application-specific optimization of FE-FETs. In addition, we show that the effective polarization–voltage characteristics of the FE layer in the FE–DE stack exhibit a negative slope region that leads to the charge enhancement effects in the FE–DE stack. While such effects are most commonly misinterpreted as either the transient effects or the stabilized single-domain negative capacitance effects, we demonstrate that the appearance of a negative slope in the hysteretic polarization–voltage characteristics is quasi-static in nature and that originates from the multi-domain polarization switching in the FE.

Ferroelectric FET Based Coupled-Oscillatory Network for Edge Detection

Abstract: Coupled-oscillatory networks are an emerging paradigm for efficiently solving optimization problems. In this work, we demonstrate the application of ferroelectric field-effect transistor (FeFET) for energy-efficient coupled-oscillatory networks. A CMOS-compatible FeFET was fabricated having > 1V of hysteresis window and 57 mV/dec of minimum subthreshold swing. With our proposed FeFET oscillator circuits and optimized biasing schemes, a $2\times $ wider synchronization range and up to $276\times $ lower energy per cycle were achieved compared to previous FeFET-based oscillators. Moreover, we employ FeFET coupled-oscillatory network for an edge detection task. Our simulations considering FeFET non-idealities and process variations with a 5-bit quantized image show that the edge detection output closely follows the ideal output.

Current annealing to improve drain output performance of β-Ga2O3 field-effect transistor

Abstract: Current annealing, which utilizes high level of drain current during device fabrication, is proposed. A semiconductor device β-Ga2O3 field-effect transistor is preferred as test vehicle because of its inherently high drain current. With just a few seconds of current annealing, drain output performance can be boosted more than 50% without adding other processes. Both electrical measurements and numerical simulations are performed to investigate the annealing behavior. Especially, proposed substrate engineering to promote thermal isolation enables better power consumption during current annealing.

The Critical Role of Charge Balance on the Memory Characteristics of Ferroelectric Field-Effect Transistors

Abstract: Ferroelectric field-effect transistors (Fe-FETs) with ferroelectric hafnium oxide (FE HfO2) as the gate insulator are being extensively explored as a promising device candidate for non-volatile memory application. FE HfO2 exhibits long retention over ten years, high endurance over 1012 cycles, high speed with subnanosecond polarization switching, and high remnant polarization of 10– $30~\mu \text{C}$ /cm2. However, the performance of Fe-FETs is known to be much worse than FE HfO2 capacitors, which is not completely understood. In this work, we developed a comprehensive Fe-FET model based on a charge balance framework. The role of charge balance and the impact of leakage-assist-switching mechanism on the memory characteristics of Fe-FETs with Metal/Ferroelectric/Dielectric/Semiconductor (M/FE/DE/S) gate-stack is studied. It is found that the ferroelectric/dielectric (FE/DE) interface and DE layer instead of FE layer is critical to determine the memory characteristics of Fe-FETs, and experimental Fe-FETs can be well explained by this model, where the discrepancy between FE capacitors and Fe-FETs are successfully understood.

Ionic control over ferroelectricity in 2D layered van der Waals capacitors.

Abstract: The van der Waals layered material CuInP2S6 features interesting functional behavior, including the existence of four uniaxial polarization states, polarization reversal against the electric field through Cu ion migration, a negative-capacitance regime, and reversible extraction of Cu ions. At the heart of these characteristics lies the high mobility of Cu ions, which also determines the spontaneous polarization. Therefore, Cu migration across the lattice results in unusual ferroelectric behavior. Here, we demonstrate how the interplay of polar and ionic properties provides a path to ionically controlled ferroelectric behavior, achieved by applying selected DC voltage pulses and subsequently probing ferroelectric switching during fast triangular voltage sweeps. Using current measurements and theoretical calculations, we observe that increasing DC pulse duration results in higher ionic currents, the build-up of an internal electric field that shifts polarization loops, and an increase in total switchable polarization by ~50% due to the existence of a high polarization phase which is stabilized by the internal electric field. Apart from tuning ferroelectric behavior by selected square pulses, hysteretic polarization switching can even be entirely deactivated and reactivated, resulting in three-state systems where polarization switching is either inhibited or can be performed in two different directions.

Bilayer Quantum Hall States in an n-Type Wide Tellurium Quantum Well.

Abstract: Tellurium (Te) is a narrow bandgap semiconductor with a unique chiral crystal structure. The topological nature of electrons in the Te conduction band can be studied by realizing n-type doping using atomic layer deposition (ALD) technique on two-dimensional (2D) Te film. In this work, we fabricated and measured the double-gated n-type Te Hall-bar devices, which can operate as two separate or coupled electron layers controlled by the top gate and back gate. Profound Shubnikov-de Haas (SdH) oscillations are observed in both top and bottom electron layers. Landau level hybridization between two layers, compound and charge-transferable bilayer quantum Hall states at filling factor ν = 4, 6, and 8, are analyzed. Our work opens the door for the study of Weyl physics in coupled bilayer systems of 2D materials.

High-Performance In₂O₃-Based 1T1R FET for BEOL Memory Application

Abstract: In this article, we report high-performance one-transistor-one-resistor (1T1R) FETs for nonvolatile memory application based on nanometer-thick indium oxide (In2O3) as channel material deposited by atomic layer deposition (ALD). ALD grown hafnium oxide (HfO2) and aluminum oxide (Al2O3) are used as gate dielectrics as well as insulator in resistive part. Two nonvolatile states with different threshold voltages are realized. High ${I}_{ \mathrm{\scriptscriptstyle ON}}/{I}_{ \mathrm{\scriptscriptstyle OFF}} > 10^{10}$ at ${V}_{\mathrm {GS}} =0$ V, large memory window (MW) exceeding 10 V, and deep sub-60-mV/dec subthreshold slope (SS) are achieved on ALD In2O3 1T1R FETs. Channel length ( ${L}_{\mathrm {ch}}$ ) and channel thickness ( ${T}_{\mathrm {ch}}$ ) dependence of device properties are systematically investigated. Optimized In2O3 thickness is determined to 1.2 nm, balancing ${I}_{ \mathrm{\scriptscriptstyle ON}}/{I}_{ \mathrm{\scriptscriptstyle OFF}}$ , MW, device variation, and stability. The fabrication process has a low thermal budget below 225 °C. Thus, these 1T1R FETs are back-end-of-line (BEOL) compatible and promising for monolithic 3-D integration to realize near-/in-memory computing.

Dynamics Studies of Polarization Switching in Ferroelectric Hafnium Zirconium Oxide

Abstract: In this paper, we review the ultrafast direct measurement on the transient ferroelectric polarization switching in hafnium zirconium oxide with crossbar metal-insulator-metal (MIM) structures including materials development, device fabrication, structure optimization and ultrafast electrical pulse measurement setup. Observation of a record low sub-nanosecond characteristic switching time of 925 ps was achieved on a single crossbar structure and a record fast polarization switching of 360 ps was achieved with 0.1 μm2 crossbar array device structure respectively. The impact of electric field, film thickness and device area on the polarization switching speed is systematically studied and the results are supported by a framework of nucleation limited switching model.

First Demonstration of Robust Tri-Gate \b{eta}-Ga2O3 Nano-membrane Field-Effect Transistors Operated Up to 400 {\deg}C

Abstract: Nano-membrane tri-gate beta-gallium oxide (\b{eta}-Ga2O3) field-effect transistors (FETs) on SiO2/Si substrate fabricated via exfoliation have been demonstrated for the first time. By employing electron beam lithography, the minimum-sized features can be defined with a 50 nm fin structure. For high-quality interface between \b{eta}-Ga2O3 and gate dielectric, atomic layer-deposited 15-nm-thick aluminum oxide (Al2O3) was utilized with Tri-methyl-aluminum (TMA) self-cleaning surface treatment. The fabricated devices demonstrate extremely low subthreshold slope (SS) of 61 mV/dec, high drain current (IDS) ON/OFF ratio of 1.5 X 109, and negligible transfer characteristic hysteresis. We also experimentally demonstrated robustness of these devices with current-voltage (I-V) characteristics measured at temperatures up to 400 °C.

High-Frequency Tellurene MOSFETs with Biased Contacts

Abstract: Microwave performance of MOSFETs with a tellurene channel is reported for the first time. The measured forward current-gain cutoff frequency and the maximum frequency of oscillation are 1.4 GHz and 3.6 GHz, respectively. Overcoming the challenge for contacting 2D materials, source contact bias is shown to increase the drain current three times and the peak transconductance four times. Additionally, tellurene being stable in air, the MOSFETs are stable for months even without surface passivation. This suggests that tellurene is a viable candidate channel material for thin-film transistors capable of operation at microwave frequencies.