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Thomas C. Oh

Researcher at HRL Laboratories

Publications -  14
Citations -  608

Thomas C. Oh is an academic researcher from HRL Laboratories. The author has contributed to research in topics: Transistor & CMOS. The author has an hindex of 8, co-authored 14 publications receiving 486 citations. Previous affiliations of Thomas C. Oh include University of California, San Diego.

Papers
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Scaling of GaN HEMTs and Schottky Diodes for Submillimeter-Wave MMIC Applications

TL;DR: In this article, the authors report state-of-the-art high frequency performance of GaN-based high electron mobility transistors (HEMTs) and Schottky diodes achieved through innovative device scaling technologies such as vertically scaled enhancement and depletion mode (E/D mode) AlN/GaN/AlGaN double-heterojunction HEMT epitaxial structures.
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>70% Power-Added-Efficiency Dual-Gate, Cascode GaN HEMTs Without Harmonic Tuning

TL;DR: In this article, the authors report the state-of-the-art performance of deep-submicrometer gate length dual-gate and cascode GaN HEMTs with $10-times reduction in gate-to-drain feedback capacitance.
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High-Speed, Enhancement-Mode GaN Power Switch With Regrown ${\rm n}+$ GaN Ohmic Contacts and Staircase Field Plates

TL;DR: In this article, a novel GaN heterojunction field effect transistor (HOFET) was reported, which has an unprecedented combination of high breakdown (176 V), low ON-resistance (1.2 Ωmm), enhancement-mode operation (VTH=+0.35 V), and excellent high-frequency performance (fT/fmax=50/120 GHz).
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Novel Asymmetric Slant Field Plate Technology for High-Speed Low-Dynamic R on E/D-mode GaN HEMTs

TL;DR: In this paper, a novel asymmetric field plate structure utilizing a slanted field plate (FP) engineered to appropriately distribute the electric field on GaN high-electron mobility transistors (HEMTs) scaled for low-loss, high-speed power switch applications is discussed.
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A High-Linearity, 30 GS/s Track-and-Hold Amplifier and Time Interleaved Sample-and-Hold in an InP-on-CMOS Process

TL;DR: A high-speed, track-and-hold amplifier and interleaved CMOS sample- and-hold circuit are implemented in an InP-on-CMOS fabrication process, yielding higher performance circuits at lower power consumption and a novel HBT buffer with feedback is demonstrated to offer high linearity and low power.