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Uddalak Bhattacharya

Researcher at Intel

Publications -  72
Citations -  3349

Uddalak Bhattacharya is an academic researcher from Intel. The author has contributed to research in topics: Static random-access memory & CMOS. The author has an hindex of 26, co-authored 70 publications receiving 3235 citations. Previous affiliations of Uddalak Bhattacharya include University of California, Santa Barbara.

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Journal ArticleDOI

A 3-GHz 70-mb SRAM in 65-nm CMOS technology with integrated column-based dynamic power supply

TL;DR: In this article, a column-based dynamic power supply has been integrated into a high-frequency 70-Mb SRAM design that is fabricated on a high performance 65-nm CMOS technology.
Proceedings ArticleDOI

A 22nm SoC platform technology featuring 3-D tri-gate and high-k/metal gate, optimized for ultra low power, high performance and high density SoC applications

TL;DR: In this paper, a leading edge 22nm 3-D tri-gate transistor technology has been optimized for low power SoC products for the first time, and a low standby power 380Mb SRAM capable of operating at 2.6GHz with 10pA/cell standby leakages.
Journal ArticleDOI

Active and nonlinear wave propagation devices in ultrafast electronics and optoelectronics

TL;DR: In this article, active and nonlinear wave propagation devices for generation and detection of (sub)millimeter wave and (sub)-picosecond signals are described, including photodetectors with sampling circuits and instrumentation for millimeter-wave waveform and network (circuit) measurements both on-wafer and in free space.
Journal ArticleDOI

Dynamic localization, absolute negative conductance, and stimulated, multiphoton emission in sequential resonant tunneling semiconductor superlattices.

TL;DR: In this article, the authors reported the first observation of absolute negative conductance and multiphoton stimulated emission in sequential resonant tunneling semiconductor superlattices driven by intense terahertz electric fields.
Journal ArticleDOI

SRAM design on 65-nm CMOS technology with dynamic sleep transistor for leakage reduction

TL;DR: In this paper, a 70-Mb SRAM was designed and fabricated on a 65-nm CMOS technology, which features a 0.57-/spl mu/m/sup 2/6T SRAM cell with large noise margin down to 0.7 V for low-voltage operation.