V
Veena Misra
Researcher at North Carolina State University
Publications - 251
Citations - 5283
Veena Misra is an academic researcher from North Carolina State University. The author has contributed to research in topics: Gate dielectric & Dielectric. The author has an hindex of 39, co-authored 249 publications receiving 4954 citations. Previous affiliations of Veena Misra include University of North Carolina at Chapel Hill & Motorola.
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Proceedings ArticleDOI
Self-powered wearable sensor platforms for wellness
Veena Misra,Ben Calhoun,Shekhar Bhansali,John Lach,Suman Datta,Mehmet Ozturk,Alper Bozkurt,Omer Oralkan,Jason Strohmaier +8 more
TL;DR: The talk will discuss the Center's latest results on energy harvesting from the human body using flexible high-performance thermo-electrics and its accomplishments in ultra-low power management units, low power chip interfaces and low power radios.
Journal ArticleDOI
Electrical Properties of Stacked RTO/RTCVD Oxides as Gate Dielectrics
TL;DR: In this paper, stacked oxides consisting of RTO and RTCVD oxides are characterized and compared to conventional LPCVD methods to form the top oxide, which produces excellent bulk and interfacial properties.
Proceedings ArticleDOI
A new AlGaN/GaN power HFET employing partial deep trench drain structure for high voltage application
TL;DR: In this article, a new AlGaN/GaN heterojuction field effect transistor (HFET) employing the partial deep trench drain structure for high voltage application has been proposed and verified successfully to achieve low leakage current and small Rdson.
Proceedings ArticleDOI
Ni/sub x/Ta/sub 1-x/Si and Ni/sub x/Pt/sub 1-x/Si ternary alloys for work function tuning on SiO/sub 2/, HfSiO/sub x/ and HfO/sub 2/ dielectrics
TL;DR: In this article, two ternary alloy silicides with tunable work function ranging between 427eV to 47eV and 48eV-to 50eV were presented for dual metal gate CMOS applications.
Proceedings ArticleDOI
Integration of multi-level copper metallization into a high performance sub-0.25 /spl mu/m CMOS technology
Suresh Venkatesan,R. Venkatraman,A. Jain,J. Mendonca,S. Anderson,M. Angyal,C. Capasso,J. Cope,P. Crabtree,Saroj Das,Janos Farkas,S. Filipiak,B. Fiordalice,Gregory Norman Hamilton,M. Herrick,H. Kawasaki,R. Islam,Charles Fredrick King,J. Klein,T. Lii,Veena Misra,K. Reid,Cindy Reidsema Simpson,B. Smith,T. Sparks,David K. Watts,E.J. Weitzman,B. Wilson +27 more
TL;DR: In this article, a sub-0.25 /spl mu/m CMOS technology was developed with six levels of planarized copper interconnects to provide high performance with low power-delay products and excellent reliability.