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Yogesh Singh Chauhan

Researcher at Indian Institute of Technology Kanpur

Publications -  328
Citations -  4763

Yogesh Singh Chauhan is an academic researcher from Indian Institute of Technology Kanpur. The author has contributed to research in topics: Transistor & MOSFET. The author has an hindex of 30, co-authored 265 publications receiving 3355 citations. Previous affiliations of Yogesh Singh Chauhan include École Normale Supérieure & Indian Institutes of Technology.

Papers
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Analysis and Compact Modeling of Negative Capacitance Transistor with High ON-Current and Negative Output Differential Resistance—Part I: Model Description

Girish Pahwa, +6 more
- 01 Dec 2016 - 
TL;DR: An accurate and computationally efficient physics-based compact model to quantitatively analyze negative capacitance FET (NCFET) for real circuit design applications and accurately captures different aspects of NCFET is presented.
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Analytical Modeling of Surface-Potential and Intrinsic Charges in AlGaN/GaN HEMT Devices

Sourabh Khandelwal, +2 more
- 23 Aug 2012 - 
TL;DR: In this paper, a surface potential-based analytical model for intrinsic charges in AlGaN/GaN high electron mobility transistor devices is presented, which is in excellent agreement with experimental data.
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Numerical Investigation of Short-Channel Effects in Negative Capacitance MFIS and MFMIS Transistors: Above-Threshold Behavior

Girish Pahwa, +2 more
- 27 Sep 2018 - 
TL;DR: In this paper, the authors analyzed the impact of length scaling on the ON-state operation of the two classes of double-gate negative capacitance transistors: metal-ferroelectric-metal-insulator-semiconductor (MFMIS) and metal- ferroelectric -insulator-, semiconductor(MFIS).
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BSIM—SPICE Models Enable FinFET and UTB IC Designs

Navid Paydavosi, +6 more
- 10 May 2013 - 
TL;DR: Two turn-key surface potential-based compact models are developed to simulate multigate transistors for integrated circuit (IC) designs and they are selected as the world's first industry-standard compact model for the FinFET.
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BSIM6: Analog and RF Compact Model for Bulk MOSFET

Yogesh Singh Chauhan, +10 more
- 01 Jan 2014 - 
TL;DR: The BSIM6 model has been extensively validated with industry data from 40-nm technology node and shows excellent source-drain symmetry during both dc and small signal analysis, thus giving excellent results during analog and RF circuit simulations.