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Institution

Telcordia Technologies

About: Telcordia Technologies is a based out in . It is known for research contribution in the topics: Network packet & Node (networking). The organization has 3097 authors who have published 4737 publications receiving 237882 citations.


Papers
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Patent
10 Jun 1996
TL;DR: In this article, a database is partitioned into public and private values, some of which public values are deemed more important than others, and then the private attribute values are electronically processed to reduce any high correlation between the public values and the private values.
Abstract: Protecting a database against the deduction of confidential values contained therein is accomplished by partitioning the database into public and private values (202), some of which public values are deemed more important than others (203). The private attribute values are electronically processed (204-226) to reduce any high correlation between the public values and the private values. Specifically the processor partitions the database (204-210) into safe tuples and unsafe tuples, which unsafe tuples have high correlative public values (216-218). The processor then selectively combines the public attribute values of the tuples (220) to camouflage such tuples from deduction of their private attribute values beyond a threshold level of uncertainty (226).

55 citations

Patent
26 Sep 1989
TL;DR: In this paper, a congestion control scheme for a connection oriented packet network is disclosed, which eliminates buffer overflow and provides congestion free communication by eliminating the clustering of packets by imposing a smoothness requirement on the packet stream of each connection at the corresponding source node.
Abstract: A congestion control scheme for a connection oriented packet network is disclosed. The congestion control scheme eliminates buffer overflow and provides congestion free communication by eliminating the clustering of packets. Clustering is eliminated by imposing a smoothness requirement on the packet stream of each connection at the corresponding source node in the packet network. The smoothness is maintained for each connection over every link traversed by a connection through use of a unique queuing strategy at the nodes wherein packets arriving at a node in an incoming frame are delayed and transmitted from the node in an adjacent outgoing frame.

55 citations

Proceedings Article
01 Jan 1987
TL;DR: A family of learning algorithms that operate on a recurrent, symmetrically connected, neuromorphic network that, like the Boltzmann machine, settles in the presence of noise and a version of the supervised learning algorithm for a network with analog activation functions.
Abstract: We describe a family of learning algorithms that operate on a recurrent, symmetrically connected, neuromorphic network that, like the Boltzmann machine, settles in the presence of noise. These networks learn by modifying synaptic connection strengths on the basis of correlations seen locally by each synapse. We describe a version of the supervised learning algorithm for a network with analog activation functions. We also demonstrate unsupervised competitive learning with this approach, where weight saturation and decay play an important role, and describe preliminary experiments in reinforcement learning, where noise is used in the search procedure. We identify the above described phenomena as elements that can unify learning techniques at a physical microscopic level. These algorithms were chosen for ease of implementation in vlsi. We have designed a CMOS test chip in 2 micron rules that can speed up the learning about a millionfold over an equivalent simulation on a VAX 11/780. The speedup is due to parallel analog computation for summing and multiplying weights and activations, and the use of physical processes for generating random noise. The components of the test chip are a noise amplifier, a neuron amplifier, and a 300 transistor adaptive synapse, each of which is separately testable. These components are also integrated into a 6 neuron and 15 synapse network. Finally, we point out techniques for reducing the area of the electronic correlational synapse both in technology and design and show how the algorithms we study can be implemented naturally in electronic systems.

55 citations

Patent
03 Feb 1998
TL;DR: In this article, a liquid crystal switching element relying upon a segmented liquid-crystal polarization modulator, at least one frequency dispersive grating and one or more polarization-dispersive elements, such as Wollaston prisms, was proposed to switch separate wavelength-divided signals among four optical paths.
Abstract: A liquid-crystal switching element relying upon a segmented liquid-crystal polarization modulator, at least one frequency-dispersive grating and one or more polarization-dispersive elements, such as Wollaston prisms, to switch separate wavelength-divided signals among four optical paths. The switching is done complementally between the fibers of each pair, and the same switching is done for the two pairs. According to the invention, all four beams can be processed by a single set of serial optics. The invention is particularly useful as an optical interconnect between two optical fiber communications wings in which each wing includes two counter-rotating fibers. The invention advantageously uses a dielectric thin-film beam splitter for one of the polarization-dispersive elements and a Wollaston prism for the other. The reflective embodiment in which a mirror replaces all the components on the output side can be improved by using two semitransparent electrode layers on the input side separated by a quarter-wavelength of dielectric.

55 citations

Patent
31 Oct 1988
TL;DR: In this article, the phase window comparator is used to determine from the phase of the output clock signal whether the phase is leading, lagging or within a prescribed window of acceptability.
Abstract: A digital phase locked loop operable over a wide dynamic range has jitter performance that is exactly bounded within predetermined limits. The phase locked loop includes an accumulator-type digital voltage controlled oscillator (201) which generates from a high speed system clock, an output clock signal at frequency equal to p times the frequency of an input clock signal, and which output frequency is controlled by the value k of a digital input to the VCO. A frequency window comparator (208) compares the number of output clock pulses between input clock pulses to determine, based on the count, whether the frequency of the output is too high, too low or equal to the correct frequency. A phase window comparator (210) simultaneously determines from the phase of the output clock signal whether the phase is leading, lagging or within a prescribed window of acceptability. In response to these determinations, k-controller (217) increases k to increase the frequency of the VCO when the frequency window comparator indicates the frequency is low or the phase window comparator indicates the phase is lagging; alternatively, k is decreased when the frequency is high or the phase is leading. Adjustment continues until the output clock is at the proper frequency and phase of the output clock falls within the window of acceptability.

55 citations


Authors

Showing all 3097 results

NameH-indexPapersCitations
Joseph E. Stiglitz1641142152469
Pete Smith1562464138819
Jean-Marie Tarascon136853137673
Ramamoorthy Ramesh12264967418
Martin Vetterli10576157825
Noga Alon10489544575
Amit P. Sheth10175342655
Harold G. Craighead10156940357
Susan T. Dumais10034660206
Andrzej Cichocki9795241471
Robert E. Kraut9729738116
Kishor S. Trivedi9569836816
David R. Clarke9055336039
Axel Scherer9073643939
Michael R. Lyu8969633257
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Performance
Metrics
No. of papers from the Institution in previous years
YearPapers
20191
20182
20171
20161
20151
20143