A Barrier Controlled Charge Plasma-Based TFET With Gate Engineering for Ambipolar Suppression and RF/Linearity Performance Improvement

TLDR: In various possibilities of devices, ATLAS device simulations show that the DMCG-CPTFET attains optimum result with three different combinations of work-functions to achieve better performance in terms of DC, analog/RF, and linearity metrics.

Abstract: To address the fabrication complexity and cost of nanoscale devices, a dual material control gate charge-plasma-based tunnel FET (DMCG-CPTFET) is presented for the first time for the suppression of ambipolarity and improvement of analog/radio frequency (RF), and linearity performance. The formation of p+ source and n+ drain regions in DMCG-CPTFET is done by the deposition of platinum (work- ${\mathrm{ function}} = 5.93$ eV) and hafnium (work- ${\mathrm{ function}} = 3.9$ eV) materials, respectively, over the silicon body. Hence, the proposed device avoids doping control issues, random dopant fluctuations, and it neither needs abrupt doping nor high thermal budget, which makes fabrication process simpler. In DMCG-CPTFET, the gate is divided into three segments, namely, tunneling gate (M1), control gate (M2), and auxiliary gate (M3) with their equivalent work functions as $\phi _{1}$ , $\phi _{2}$ , and $\phi _{3}$ , respectively. However, we have explored three different combinations of work-functions to achieve better performance in terms of DC, analog/RF, and linearity metrics. In various possibilities of devices, ATLAS device simulations show that the DMCG-CPTFET attains optimum result with $\phi _{1} = \phi _{3} , where $\phi _{1}$ is used at source side to improve the ON-state current, whereas $\phi _{3}$ (same as $\phi _{1}$ ) is considered at drain side in order to suppress the ambipolarity.