Journal ArticleDOI
A new technique for on-chip error estimation and reconfiguration of current-steering digital-to-analog converters
K.P.S. Rafeeque,Vinita Vasudevan +1 more
TLDR
A novel technique for estimation of DNL based on a step-size measurement is proposed, which greatly reduces the linearity and dynamic range requirements of the measuring circuits.Abstract:
In this paper, we propose a reconfigurable current-steering digital-to-analog converter (DAC). The differential nonlinearity error (DNL) of the DAC is estimated on-chip. This is used to reconfigure the switching sequence to get a lower integral nonlinearity error (INL). We propose a novel technique for estimation of DNL based on a step-size measurement. This greatly reduces the linearity and dynamic range requirements of the measuring circuits. A 10-b segmented DAC, along with the associated circuits for DNL estimation and reconfiguration, was designed using 0.35-/spl mu/m CMOS technology and fabricated through Europractice. The paper includes theoretical analysis, simulation, and experimental results for the proposed technique.read more
Citations
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Journal ArticleDOI
A 14 bit 200 MS/s DAC With SFDR >78 dBc, IM3 < -83 dBc and NSD <-163 dBm/Hz Across the Whole Nyquist Band Enabled by Dynamic-Mismatch Mapping
Yongjian Tang,J. Briaire,Kostas Doris,R.H.M. van Veldhoven,P.C.W. van Beek,Hans Hegt,A.H.M. van Roermund +6 more
TL;DR: By optimizing the switching sequence of current cells to reduce the dynamic integral nonlinearity in an I-Q domain, the DMM technique digitally calibrates all mismatch errors so that both the DAC static and dynamic performance can be significantly improved in a wide frequency range.
Journal ArticleDOI
A 10-bit DC-20-GHz Multiple-Return-to-Zero DAC With >48-dB SFDR
Lucas Duncan,Brian Dupaix,Jamin J. McCue,Brandon Mathieu,Matthew LaRue,Vipul J. Patel,Mesfin Teshome,Myung-Jun Choe,Waleed Khalil +8 more
TL;DR: To minimize frequency-dependent amplitude and phase errors in the output summing node, which can dominate linearity performance at GHz and mm-wave frequencies, a vertically stacked tree (VST) and feed-forward (FF) path are proposed.
Proceedings ArticleDOI
A 14b 200MS/s DAC with SFDR>78dBc, IM3<−83dBc and NSD<−163dBm/Hz across the whole Nyquist band enabled by dynamic-mismatch mapping
Yongjian Tang,J. Briaire,Kostas Doris,Robert van Veldhoven,Pieter C. W. van Beek,Hans Hegt,Arthur van Roermund +6 more
TL;DR: A 14-bit 200MS/s current-steering DAC with a novel digital calibration technique called dynamic-mismatch mapping (DMM) is presented, which reduces the nonlinearities caused by both amplitude and timing errors, without noise penalty.
Journal ArticleDOI
Dual-Calibration Technique for Improving Static Linearity of Thermometer DACs for I/O
TL;DR: A dual-calibration technique to improve the matching accuracy of digital-to-analog converter (DAC) elements and improve nonlinearity induced static errors in a current-steering thermometer DAC is proposed.
References
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Journal ArticleDOI
Gradient error cancellation and quadratic error reduction in unary and binary D/A converters
TL;DR: A novel geometrical arrangement of unit cells in a digital-analog converter (D/A) converter, along with a new switching sequence results in full cancellation of gradient errors, thus improving D/A performance.
Journal ArticleDOI
A cost-effective approach to the design and layout of a 14-b current-steering DAC macrocell
TL;DR: This brief discusses the economical design of a 14-b current-steering digital-to-analog converter (DAC) macrocell for integration with other analog and digital macrocells in a system-on-chip (SOC).
Proceedings ArticleDOI
Error detection and analysis in self-testing data conversion systems employing charge-redistribution techniques
C.A. Leme,J.E. Franca +1 more
TL;DR: Results on the self-testing capabilities of multiplexed data conversion systems based on charge-redistribution techniques in binary-weighted capacitor arrays are presented and a low-cost quality control can be easily be implemented.