Journal ArticleDOI
A new technique for on-chip error estimation and reconfiguration of current-steering digital-to-analog converters
K.P.S. Rafeeque,Vinita Vasudevan +1 more
TLDR
A novel technique for estimation of DNL based on a step-size measurement is proposed, which greatly reduces the linearity and dynamic range requirements of the measuring circuits.Abstract:
In this paper, we propose a reconfigurable current-steering digital-to-analog converter (DAC). The differential nonlinearity error (DNL) of the DAC is estimated on-chip. This is used to reconfigure the switching sequence to get a lower integral nonlinearity error (INL). We propose a novel technique for estimation of DNL based on a step-size measurement. This greatly reduces the linearity and dynamic range requirements of the measuring circuits. A 10-b segmented DAC, along with the associated circuits for DNL estimation and reconfiguration, was designed using 0.35-/spl mu/m CMOS technology and fabricated through Europractice. The paper includes theoretical analysis, simulation, and experimental results for the proposed technique.read more
Citations
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Journal ArticleDOI
A 14 bit 200 MS/s DAC With SFDR >78 dBc, IM3 < -83 dBc and NSD <-163 dBm/Hz Across the Whole Nyquist Band Enabled by Dynamic-Mismatch Mapping
Yongjian Tang,J. Briaire,Kostas Doris,R.H.M. van Veldhoven,P.C.W. van Beek,Hans Hegt,A.H.M. van Roermund +6 more
TL;DR: By optimizing the switching sequence of current cells to reduce the dynamic integral nonlinearity in an I-Q domain, the DMM technique digitally calibrates all mismatch errors so that both the DAC static and dynamic performance can be significantly improved in a wide frequency range.
Journal ArticleDOI
A 10-bit DC-20-GHz Multiple-Return-to-Zero DAC With >48-dB SFDR
Lucas Duncan,Brian Dupaix,Jamin J. McCue,Brandon Mathieu,Matthew LaRue,Vipul J. Patel,Mesfin Teshome,Myung-Jun Choe,Waleed Khalil +8 more
TL;DR: To minimize frequency-dependent amplitude and phase errors in the output summing node, which can dominate linearity performance at GHz and mm-wave frequencies, a vertically stacked tree (VST) and feed-forward (FF) path are proposed.
Proceedings ArticleDOI
A 14b 200MS/s DAC with SFDR>78dBc, IM3<−83dBc and NSD<−163dBm/Hz across the whole Nyquist band enabled by dynamic-mismatch mapping
Yongjian Tang,J. Briaire,Kostas Doris,Robert van Veldhoven,Pieter C. W. van Beek,Hans Hegt,Arthur van Roermund +6 more
TL;DR: A 14-bit 200MS/s current-steering DAC with a novel digital calibration technique called dynamic-mismatch mapping (DMM) is presented, which reduces the nonlinearities caused by both amplitude and timing errors, without noise penalty.
Journal ArticleDOI
Dual-Calibration Technique for Improving Static Linearity of Thermometer DACs for I/O
TL;DR: A dual-calibration technique to improve the matching accuracy of digital-to-analog converter (DAC) elements and improve nonlinearity induced static errors in a current-steering thermometer DAC is proposed.
References
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Journal ArticleDOI
A 10-b 70-MS/s CMOS D/A converter
TL;DR: In this paper, a 10-b 70-MS/s CMOS D/A converter fabricated in a 1- mu m CMOS technology is described, where an integral linearity error caused by error distributions of current sources is reduced by a new switching sequence called hierarchical symmetrical switching.
Proceedings ArticleDOI
A BIST scheme for on-chip ADC and DAC testing
TL;DR: This paper discusses on-chip generation of linear ramps as test stimuli, and proposes techniques for measuring the DNL and INL of the converters, and validates the scheme with software simulation-5% LSB test accuracy can be achieved in the presence of reasonable analog imperfection.
Journal ArticleDOI
Switching sequence optimization for gradient error compensation in thermometer-decoded DAC arrays
Yonghua Cong,Randall L. Geiger +1 more
TL;DR: In this paper, switching schemes for gradient error compensation in unary (thermometer-decoded) arrays of digital-to-analog converters (DACs) are discussed.
Proceedings ArticleDOI
An accurate statistical yield model for CMOS current-steering D/A converters
TL;DR: A formula is derived that allows us to accurately describe the impact of the mismatch on the INL (integral non-linearity) yield of current-steering D/A converters without any loss of design time.
Journal ArticleDOI
New frequency-locked loop based on CMOS frequency-to-voltage converter: design and implementation
TL;DR: In this paper, the authors describe the architecture of a new CMOS fully integrated frequency-locked loop (FLL), which contains a frequency-to-voltage converter (FVC), an operational amplifier (opamp) and a differential voltage-controlled oscillator (VCO).