scispace - formally typeset
Journal ArticleDOI

A Vertical Power MOSFET With an Interdigitated Drift Region Using High- $k$ Insulator

TLDR
In this paper, a vertical power MOSFET with an interdigitated drift region using high- $k$ (Hk) insulator was studied and it was shown that the specific on-resistance of the Hk-MOSET is comparable to that of the superjunction MOSET with the same breakdown voltage.
Abstract
A vertical power MOSFET with an interdigitated drift region using high- $k$ (Hk) insulator (Hk-MOSFET) is studied. Due to the fact that most of the electric displacement lines produced by the charges of the depleted drift region under reverse bias are through the Hk insulator, much heavier doping concentration can be used in the drift region when comparing with a conventional MOSFET with the same breakdown voltage. It is shown that the specific on-resistance of the Hk-MOSFET is comparable to that of the superjunction MOSFET (SJ-MOSFET) with the same breakdown voltage. The turn-on and turn-off times are found to be little longer than those of the conventional MOSFET and the SJ-MOSFET. The theoretical results of the electrical characteristics are in good agreement with the results from numerical simulations.

read more

Citations
More filters
Journal ArticleDOI

Variation of Lateral Width Technique in SoI High-Voltage Lateral Double-Diffused Metal–Oxide–Semiconductor Transistors Using High-k Dielectric

TL;DR: By employing the linear increasing drift region width and the high-k dielectric region, a novel variation of lateral width (VLW) technique is proposed to even the equipotential contour and increase the drift doping concentration, which maximize the breakdown voltage and reduce the specific ON-resistance as discussed by the authors.
Journal ArticleDOI

Ultralow ON-Resistance SOI LDMOS With Three Separated Gates and High- $k$ Dielectric

TL;DR: In this article, a novel ultralow specific on-resistance ( $R_{\mathrm{\scriptscriptstyle ON},\text {sp}})$ SOI lateral double-diffused MOS (LDMOS) with three separated gates (TSGs) and high- $k$ (HK) pillars is proposed and investigated by simulation.
Journal ArticleDOI

Novel Superjunction LDMOS With a High- K Dielectric Trench by TCAD Simulation Study

TL;DR: In this article, a superjunction lateral double-diffused MOSFET with a deep High-K (HK) dielectric trench (HK SJ-LDMOS) is proposed and its mechanism is investigated by Technology Computer Aided Design (TCAD) simulations.
Journal ArticleDOI

Vertical Power ${\rm H}k$ -MOSFET of Hexagonal Layout

TL;DR: In this paper, a vertical power MOSFET with hexagonal cells by using high-k insulator (Hk-MOSFet) in voltage-sustaining region is studied.
Journal ArticleDOI

Novel SiC/Si Heterojunction Power MOSFET With Breakdown Point Transfer Terminal Technology by TCAD Simulation Study

TL;DR: In this paper, a SiC/Si heterojunction power MOSFET was proposed to improve the tradeoff between the breakdown voltage (BV) and specific on-resistance (R}_{ \mathrm{ON},\textsf {sp}}$ ).
References
More filters
Patent

Semiconductor power devices with alternating conductivity type high-voltage breakdown regions

TL;DR: In this article, the CB-layer was introduced, where two kinds of semiconductor regions with opposite types of conduction are alternatively arranged, viewed from any cross-section parallel to the interface between the layer itself and the n + (or p + )-region.
Patent

High voltage semiconductor device

TL;DR: In this article, a depletion layer formed throughout a portion in at least a high voltage mode of operation of the device, such as, by reverse biasing a rectifying junction, was introduced.
Journal ArticleDOI

Calculation of avalanche breakdown voltages of silicon p-n junctions

TL;DR: An empirical formula for the ionization coefficient given by α = CEg (C and g constants, E electric field) and which is considered as a common effective value for both holes and electrons yields tractable expressions for the breakdown voltages of abrupt and graded silicon pn junctions.
Journal ArticleDOI

Optimization of the specific on-resistance of the COOLMOS/sup TM/

TL;DR: In this paper, the physical and geometrical parameters of the p- and n-regions used in the voltage-sustaining layer of the COOLMOS/sup TM/ are presented.
Journal ArticleDOI

Theory of a novel voltage-sustaining layer for power devices

TL;DR: The Composite Buffer layer (CB-layer for short) as mentioned in this paper is a voltage-sustaining layer for power devices, which consists of alternating n- and p-type regions that are parallel to the direction of the applied electric field.
Related Papers (5)