Journal ArticleDOI
High-Level Synthesis: Past, Present, and Future
Grant Martin,G. Smith +1 more
TLDR
The authors offer insights on why earlier attempts to gain industry adoption were not successful, why current HLS tools are finally seeing adoption, and what to expect as HLS evolves toward system-level design.Abstract:
This article presents the history and evolution of HLS from research to industry adoption. The authors offer insights on why earlier attempts to gain industry adoption were not successful, why current HLS tools are finally seeing adoption, and what to expect as HLS evolves toward system-level design.read more
Citations
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Proceedings ArticleDOI
SCNN: An Accelerator for Compressed-sparse Convolutional Neural Networks
Angshuman Parashar,Minsoo Rhu,Anurag Mukkara,Antonio Puglielli,Rangharajan Venkatesan,Brucek Khailany,Joel Emer,Stephen W. Keckler,William J. Dally +8 more
TL;DR: The Sparse CNN (SCNN) accelerator as discussed by the authors employs a dataflow that enables maintaining the sparse weights and activations in a compressed encoding, which eliminates unnecessary data transfers and reduces storage requirements.
Journal ArticleDOI
Designing Custom Arithmetic Data Paths with FloPoCo
F. de Dinechin,Bogdan Pasca +1 more
TL;DR: This work presents a leading effort to automate the production of pipelined data-path circuits for implementing numerical functions in FPGA-based acceleration of scientific computing.
Book
The Zynq Book: Embedded Processing with the Arm Cortex-A9 on the Xilinx Zynq-7000 All Programmable Soc
TL;DR: This book is about the Zynq-7000 All Programmable System on Chip, the family of devices from Xilinx that combines an application-grade ARM Cortex-A9 processor with traditional FPGA logic fabric.
Posted Content
SCNN: An Accelerator for Compressed-sparse Convolutional Neural Networks
Angshuman Parashar,Minsoo Rhu,Anurag Mukkara,Antonio Puglielli,Rangharajan Venkatesan,Brucek Khailany,Joel Emer,Stephen W. Keckler,William J. Dally +8 more
TL;DR: The Sparse CNN (SCNN) accelerator architecture is introduced, which improves performance and energy efficiency by exploiting thezero-valued weights that stem from network pruning during training and zero-valued activations that arise from the common ReLU operator.
Proceedings ArticleDOI
On learning-based methods for design-space exploration with high-level synthesis
Hung-Yi Liu,Luca P. Carloni +1 more
TL;DR: A study on the application of learning-based methods for the DSE problem is presented, and a learning model for HLS that is superior to the best models described in the literature is proposed.
References
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Book
Synthesis and optimization of digital circuits
TL;DR: This book covers techniques for synthesis and optimization of digital circuits at the architectural and logic levels, i.e., the generation of performance-and-or area-optimal circuits representations from models in hardware description languages.
Book
High ― Level Synthesis: Introduction to Chip and System Design
TL;DR: This paper presents a methodology for High-Level Synthesis of Architectural Models in Synthesis and its applications in Design Description Languages and Design Representation and Transformations.
Journal ArticleDOI
Force-directed scheduling for the behavioral synthesis of ASICs
P.G. Paulin,J.P. Knight +1 more
TL;DR: A general scheduling methodology is presented that can be integrated into specialized or general-purpose high-level synthesis systems and reduces the number of functional units, storage units, and buses required by balancing the concurrency of operations assigned to them.
Book
High-Level Synthesis: from Algorithm to Digital Circuit
Philippe Coussy,Adam Morawiec +1 more
TL;DR: This book presents an excellent collection of contributions addressing different aspects of high-level synthesis from both industry and academia, and should be on each designers and CAD developers shelf.