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Journal ArticleDOI

IC power delivery: Voltage regulation and conversion, system-level cooptimization and technology implications

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TLDR
A systematic design analysis on power delivery networks that incorporate Buck Converters and on-chip Low-Dropout voltage regulators for the entire chip power supply shows significant performance improvements in terms of achievable area overhead, supply noise and power efficiency.
Abstract
Modern IC power delivery systems encompass large on-chip passive power grids and active on-chip or off-chip voltage converters and regulators. While there exists little work targeting on holistic design of such complex IC subsystems, the optimal system-level design of power delivery is critical for achieving power integrity and power efficiency. In this article, we conduct a systematic design analysis on power delivery networks that incorporate Buck Converters (BCs) and on-chip Low-Dropout voltage regulators (LDOs) for the entire chip power supply. The electrical interactions between active voltage converters, regulators as well as passive power grids and their influence on key system design specifications are analyzed comprehensively. With the derived design insights, the system-level codesign of a complete power delivery network is facilitated by a proposed automatic optimization flow in which key design parameters of buck converters and on-chip LDOs as well as on-chip decoupling capacitance are jointly optimized. The experimental results demonstrate significant performance improvements resulted from the proposed system cooptimization in terms of achievable area overhead, supply noise and power efficiency. Impacts of different decoupling capacitance technologies are also investigated.

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Citations
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Parallel CAD: Algorithm Design and Programming Special Section Call for Papers TODAES: ACM Transactions on Design Automation of Electronic Systems

TL;DR: This journal special section will cover recent progress on parallel CAD research, including algorithm foundations, programming models, parallel architectural-specific optimization, and verification, as well as other topics relevant to the design of parallel CAD algorithms and software tools.
Proceedings Article

Area-efficient linear regulator with ultra-fast load regulation

TL;DR: In this paper, the authors demonstrate a fully integrated linear regulator for multisupply voltage microprocessors implemented in a 90 nm CMOS technology, which enables a 90 mVp-p output droop for a 100mA load step with only a small on-chip decoupling capacitor of 0.6 nF.
Journal ArticleDOI

Multiharmonic Small-Signal Modeling of Low-Power PWM DC-DC Converters

TL;DR: This work proposes a multiharmonic model that provides a complete small-signal characterization of both DC averages and high-order harmonic responses and corrects the misleading results of the existing models by providing truthful characterization of the overall converter AC response.
Journal ArticleDOI

Optimal Allocation of LDOs and Decoupling Capacitors within a Distributed On-Chip Power Grid

TL;DR: The number, size, and location of parallel low-dropout (LDO) regulators and intentional decoupling capacitors are optimized using mixed integer non-linear programming formulation and the results are compared with a sample ISPD’11 benchmark circuits in a case study.
Patent

Methods for distributing power in layout of ic

TL;DR: In this article, a method for distributing power in the layout of an integrated circuit is provided, where the integrated circuit includes at least one macro block and the macro block includes a plurality of standard cells.
References
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Book

CMOS Analog Circuit Design

TL;DR: In this article, the authors present a simple MOS LARGE-SIGNAL MODEL (SPICE Level 1) and a small-signal model for the MOS TRANSISTOR.
Journal ArticleDOI

Area-efficient linear regulator with ultra-fast load regulation

TL;DR: In this article, the authors demonstrate a fully integrated linear regulator for multisupply voltage microprocessors implemented in a 90 nm CMOS technology, which enables a 90 mV/sub P-P/output droop with only a small on-chip decoupling capacitor of 0.6 nF.
Journal ArticleDOI

Full On-Chip CMOS Low-Dropout Voltage Regulator

TL;DR: In this article, the authors proposed a solution to the present bulky external capacitor low-dropout (LDO) voltage regulators with an external capacitorless LDO architecture, where the large external capacitor used in typical LDOs is removed allowing for greater power system integration for system-on-chip (SoC) applications.

Parallel CAD: Algorithm Design and Programming Special Section Call for Papers TODAES: ACM Transactions on Design Automation of Electronic Systems

TL;DR: This journal special section will cover recent progress on parallel CAD research, including algorithm foundations, programming models, parallel architectural-specific optimization, and verification, as well as other topics relevant to the design of parallel CAD algorithms and software tools.
Journal ArticleDOI

A capacitor-free CMOS low-dropout regulator with damping-factor-control frequency compensation

TL;DR: In this paper, a 1.5-V 100-mA capacitor-free CMOS low-dropout regulator (LDO) for system-on-chip applications to reduce board space and external pins is presented.
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