Improved Power Modeling of DDR SDRAMs
Karthik Chandrasekar
Computer Engineering
TU Delft, The Netherlands
Email: k.chandrasekar@tudelft.nl
Benny Akesson, Kees Goossens
Electronic Systems
TU Eindhoven, The Netherlands
Email: {k.b.akesson, k.g.w.goossens}@tue.nl
Abstract— Power modeling and estimation has become one of
the most defining aspects in designing modern embedded systems.
In this context, DDR SDRAM memories contribute significantly
to system power consumption, but lack accurate and generic
power models. The most popular SDRAM power model provided
by Micron, is found to be inaccurate or insufficient for several
reasons. First, it does not consider the power consumed when
transitioning to power-down and self-refresh modes. Second, it
employs the minimal timing constraints between commands from
the SDRAM datasheets and not the actual duration between
the commands as issued by an SDRAM memory controller.
Finally, without adaptations, it can only be applied to a memory
controller that employs a close-page policy and accesses a single
SDRAM bank at a time. These critical issues with Micron’s power
model impact the accuracy and the validity of the power values
reported by it and resolving them, forms the focus of our work.
In this paper, we propose an improved SDRAM power model
that estimates power consumption during the state transitions to
power-saving states, employs an SDRAM command trace to get
the actual timings between the commands issued and is generic
and applicable to all DDRx SDRAMs and all memory controller
policies and all degrees of bank interleaving. We quantitatively
compare the proposed model against the unmodified Micron
model on power and energy for DDR3-800. We show differences
of up to 60% in energy-savings for the precharge power-down
mode for a power-down duration of 14 cycles and up to 80% for
the self-refresh mode for a self-refresh duration of 560 cycles.
Index Terms—DDR SDRAMs; Power Modeling; Power Es-
timation; State Transitions; Power-Down; Self-Refresh; Bank-
Interleaving; Open-page; Close-page; SDRAM Command Trace;
I. INTRODUCTION AND MOTIVATION
Design-time and run-time power estimation is often used
for obtaining power/performance trade-offs, as per the de-
sign requirements of modern embedded Systems-On-Chip
(SoCs). DDR SDRAM memories contribute considerably to
SoC power consumption [4] and accurate power analysis of
SDRAMs is critical for defining their run-time power manage-
ment policies and for overall SoC design space exploration.
For this purpose, Micron’s SDRAM power model [1] is a
widely accepted and employed tool. However, it is found to
be inaccurate or insufficient for several reasons including:
1) It does not consider the power consumed during the state
transitions from any arbitrary SDRAM state to the power-
down and self-refresh states, reporting optimistic power saving
numbers for these modes. Schmidt et al., also empirically
verified this shortcoming of Micron’s power model in [2].
2) It employs the minimal timing constraints between suc-
cessive commands from SDRAM datasheets [13], [14] and not
the actual duration between them as issued by an SDRAM
controller, which may well be greater than the minimum con-
straints. Direct scaling of the power estimates obtained from
Micron’s power model gives pessimistic power consumption
values for basic SDRAM operations, such as reads and writes.
3) It cannot directly provide power consumption values
when an open-page policy or a multi-bank-interleaved memory
access policy [19] is employed. This is because, it assumes a
close-page policy by default and is directly applicable only
when a single SDRAM bank is accessed. When multiple
banks are accessed in parallel, Micron’s power model requires
adaptations for proper power and energy estimation.
4) It does not take into account the power consumed during
the pre-refresh clock cycles used to precharge all banks before
executing a Refresh, as a part of Refresh power.
This paper addresses all of the aforementioned issues by
proposing an improved SDRAM power model for all DDRx
SDRAMs. The proposed power model takes into account all
possible state transitions from any arbitrary SDRAM state to
the power-down and self-refresh states based on JEDEC spec-
ifications [15] [16]. Our generic power model accepts a cycle-
accurate SDRAM command trace of any length (from a single
transaction to an entire application trace) from any memory
controller, supporting both open and close-page policies and
any degree of bank-interleaving memory access scheme. Our
proposed power model employs the actual timings between
commands obtained from any such SDRAM command trace,
in combination with the measured current and voltage values
reported by memory vendors in SDRAM datasheets. Current
users of Micron’s model, such as DRAMSim [17] and Mem-
Scale [7], can benefit from our proposed power model, as it can
report improved SDRAM energy estimates for any window of
analysis (from a single transaction to an entire application).
The remainder of this paper is organized as follows: Sec-
tion II discusses the related work in power modeling of
SDRAMs. Section III gives the background information on
SDRAM organization, operation and timing constraints. Sec-
tion IV describes our approach to deriving the proposed power
model. In Section V, we propose power equations for the
basic power components to address issues (2) to (4) mentioned
above. We then address the issue of state transitions to power-
down modes and the self-refresh mode in Sections VI, VII
and VIII. Specifically, Section VI provides power equations
for the transitions from the stand-by (idle) mode to the power-
down modes. Section VII addresses transitions from any
arbitrary active mode of the memory to the power-down modes
and Section VIII discusses the transitions to the self-refresh
mode. In Section IX, we compare our power model against
Micron’s for different memory states and transitions and for
an H.263 video decoder application. Section X concludes the
paper, highlighting the significance of our contributions.
II. RELATED WORK
Micron’s SDRAM power model [1] is most widely accepted
and has several current users including the likes of DRAM-
Sim [17], MemScale [7] and [12]. However, it is found to
be inaccurate or insufficient mainly due to the four issues
discussed in Section I. Schmidt et al., in [2] and [3] empirically
measured the power values from a DDR SDRAM and showed
that Micron’s power model provided approximate and worst-
case power consumption numbers and over-estimated the
actual savings of the Self-Refresh mode for SDRAMs. They
also attributed these discrepancies to the fact that Micron’s
power model does not cover the state transitions to the Self-
Refresh or the other power saving modes and verified this
using different benchmark applications.
Other existing SDRAM power models suggested by Raw-
son [5], Joshi et al. [6] and Ji et al. [9], propose similar
SDRAM power modeling like Micron, but none of them
identified or addressed the state transitions issue and hence,
do not provide any improved power estimation numbers. On
the other hand, Joo et al. in [8] employed an energy state
machine for SDRAMs and derived energy coefficients for the
different memory states and state transitions to obtain more
accurate power estimates. However, their power model cannot
directly employ an SDRAM command trace and obtain the
actual timings between the commands, and therefore, cannot
be used to obtain accurate power estimates.
Memory power estimation tools like CACTI [11] can
provide more accurate power consumption values than the
other analytical power models and can be used for evaluating
different memory features during the design space exploration
of memory architectures. However, CACTI requires detailed
understanding of memory architectures and cannot be em-
ployed for obtaining run-time memory power estimates for a
given application, which is what is required by SoC designers.
Another promising tool by Thomas Vogelsang at Rambus
Inc [10], also aims to provide accurate power consumption
numbers for every component in the DRAM architecture. It
employs device-level details and technology specifications to
calculate the power numbers based on the switching activ-
ities and associated frequency of operation. However, since
memory vendors do not provide easy access to such detailed
specifications for their SDRAM memory architectures, the
use of this model is very limited. Hence, the most viable
method of estimating SDRAM power consumption in an SoC,
is still to use the current and voltage values from the SDRAM
datasheets [13], [14] that are based on real measurements, as
used by Micron and us. However, it should be kept in mind
that the correctness of the power model using these current
measures, defines the accuracy of the reported power values.
In this paper, we propose an accurate and generic SDRAM
power model that employs these measured current and volt-
age values from SDRAM datasheets, to provide transaction-
accurate design-time and run-time power and energy estimates.
Our proposed power model employs the actual timings be-
tween commands from an SDRAM commands trace, caters to
all DDRx SDRAM memories and all memory controllers with
any arbitrary scheduling policy and provides accurate power
and energy estimates for any window of analysis.
III. SDRAM O
RGANIZATION AND OPERATION
This section introduces the generic SDRAM architecture, its
operation and the associated timing constraints [18], for better
understanding of the proposed power model.
SDRAMs are organized in banks, rows and columns, as
shown in Figure 1. A bank includes memory elements (cells)
arranged in a matrix structure and a row buffer (with sense
amplifiers) to store contents of an active memory row. The
banks in an SDRAM operate in a parallel and pipelined
fashion, though only one bank can perform an I/O operation at
a particular instance in time and only one SDRAM command
may be issued to the memory per clock cycle. The memory
may operate in active, idle or power-down state and can have
one or more banks active in parallel, based on the degree of
bank-interleaving employed by the memory controller.
Fig. 1. SDRAM Architecture
The basic SDRAM commands issued to the memory (shown
in Figure 1) include the following:
(a) A Precharge (PRE) command: Precharges the bit lines
(columns) across all the memory rows to the reference voltage
level and restores the contents of the row buffer (if any) back
into the memory array.
(b) An Activate (ACT) command: Activates the word line of
the indicated memory row and transfers the contents from the
memory cells in that row to the row buffer for further access.
(c) A Read (RD) command: Reads out a burst of data (Burst
Length of 4 or 8 words) from the row buffer.
(d) A Write (WR) command: Writes the accompanying burst
of data (4 or 8 words) to the specified columns in row buffer.
(e) A Refresh (REF) command: Refreshes the rows in the
memory at regular intervals to recharge the memory cells to
retain the data in the memory.
In addition to these commands, it is also possible to tran-
sition to power-down state by disabling the clock at run-time
to reduce power consumption, if the memory is not in use. It
is also possible to retain the memory contents in the power-
down state by employing the Self-Refresh feature, to refresh
the memory at significantly lower power consumption.
For proper SDRAM operation, the commands discussed
above must be issued by the memory controller in a specific
order, while satisfying the associated timing constraints (for
DDR2 [15] and for DDR3 [16]). For instance, between issuing
an Activate and a Read command, the minimum timing con-
straint of tRCD should be respected. Some of these constraints
that need to be satisfied when issuing commands to a DDR3-
800 memory [14] are specified in Table I:
TABLE I
M
ICRON DDR3-800 TIMING CONSTRAINTS
Constraint Description (Minimum Time between) Time (cycles)
tRC Two ACTs to the same bank 20
tRAS An ACT and a PRE to the same bank 15
tRCD An ACT and a RD/WR to the same bank 5
tRP A PRE and next ACT to the same bank 5
tRFC A REF and the next ACT 44
These timing constraints obtained from the datasheets are
the minimal timings between two commands. However, most
SDRAM controllers do not always issue commands as soon as
these minimal constraints are satisfied. Instead, they schedule
commands based on different command scheduling and row-
buffer management policies, where the actual duration between
any two issued commands may be greater than the minimum.
For instance, the memory controller may employ an open-page
policy [18] and delay issuing a precharge to a bank until there
is a row-miss on the subsequent access to that bank.
In general, memory controllers decide to employ the open-
page policy or the close-page policy [18] based on the presence
or absence of data locality in the target application. The
former policy keeps the row buffer active to reduce the access
time for subsequent accesses to the same memory row in
the same bank, by not issuing a Precharge command at the
end of a transaction. The latter policy strictly closes the
active row buffer at the end of every transaction to a bank
with a Precharge command, for faster accesses to any other
random location in the memory in the subsequent transaction.
Additionally, read and write transactions can also be issued
with an auto-precharge flag to automatically precharge as soon
as the transaction completes. Our generic power model is
devised to support both these row-buffer management policies.
IV. O
UR APPROAC H
In this paper, we present equations to accurately model
power consumption of different SDRAM operations and es-
timate power savings for the different power-down modes
and the self-refresh mode. For this, we employ the actual
timing durations between successive commands issued by an
SDRAM controller (obtained using an SDRAM command
trace), instead of the minimal timing constraints from the
datasheets, as employed by Micron [1]. We take into account
the power consumed during the state transitions from any
arbitrary active/idle mode to the power-down mode and from
an idle state to the self-refresh mode. In short, we propose a
generic power model that is applicable to all DDRx SDRAM
memories and can be used with any memory controller using
any row-buffer management policy (open-page or close-page),
any command scheduling policy, and any degree of bank
parallelism or interleaving. We achieve this by employing a
five-step approach, as described below:
1. We execute a given application on a cycle-accurate
instruction set simulator and filter the accesses to the SDRAM
memory. These are forwarded to the SDRAM memory con-
troller, where the memory commands with all the relevant
signals are logged, to get the SDRAM command trace.
2. We the employ this SDRAM command trace to get the
actual timings between commands, as opposed to the minimum
timings from the datasheets.
3. We observe the changes in the signals to the memory in
the logged trace, to identify the state transitions and the usage
of the power-saving modes.
4. We identify the current values for the states and state
transitions using JEDEC specs and the signals to the memory.
5. We derive the power consumption values for the different
SDRAM states and state transitions, using all the details and
specifications collected in steps (1) to (4).
To identify appropriate current consumption values for the
different state transitions to the power-down or self-refresh
mode, we observe: (a) the state the memory is in (ac-
tive/precharged) before entering the power-down/self-refresh
mode, (b) the state it is expected to be in (active/precharged)
after powering back up or after exiting the self-refresh mode,
and (c) the changes to the CKE (Clock Enable) signal. We
obtain the timing requirements for those state transitions
from the JEDEC specified requirements (shown for DDR3 in
Figure 2), identify the duration of the transitions from the trace
and accurately calculate their energy consumption. Using this
approach, we obtain the power consumption values for any
such transition and compare our estimates against Micron’s.
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Fig. 2. DDR3 Power-Down Transitions and Power Consumption
As shown in the figure, tCPDED, tCKE, tXP and tXPDLL
contribute to the transition periods when switching to the
power-down mode. Micron’s model assumes the power-down
current consumption (C
PD
) for both the transition period and
the actual power-down period (tPD) (as indicated by the solid
line at the bottom in Figure 2). We corrected this flaw, and
identified the correct current consumption (C
Trans
) (shown by
the dotted line at the bottom in Figure 2) for the transition
periods. The shaded area in Figure 2, refers to the difference
in the current estimates reported by Micron and our model
during the clock cycles covering this transition period.
When it comes to regular transactions, Micron’s model
employs the minimal timing constraints (Table I) like tRC
(minimum duration between two Activates to the same bank),
as the transaction length to calculate power consumption for
the transaction. We instead propose to employ the actual
transaction length denoted by (tRC
new
) for every individual
transaction, as observed in the command trace of an SDRAM
memory controller, to calculate the exact power consumption
for that particular transaction. Note: tRC
new
is used to represent
the transaction length for all transactions and should not be
misread as being the actual timing between two ACTs to the
same bank, instead of tRC. All the actual timing parameters
are hereafter referred with a suffix ‘new’ and the minimal
timing parameters, without this suffix. Note: In the context of
our power model, a read or write transaction ends when the
corresponding data transfer or the associated auto-precharge
(if any) finishes. Similarly, an idle transaction is defined by
the duration of the continuous period of idle clock cycles.We
further clarify on the transaction lengths associated with every
operation, as and when we discuss them.
Micron’s model [1] assumes that an Activate is always
followed by a Precharge (close-page policy) in every trans-
action, at the end of the minimum active period tRAS. This
assumption rules out other policies like the open-page policy,
where a Precharge is not always used in every transaction and
the active period and the transaction length may be longer
than the minimum. Our generic model addresses this issue
by estimating power consumption of a transaction on a case-
by-case basis, where a transaction may or may not have an
Activate and/or a Precharge command (open-page policy). Our
model also addresses scenarios when two or more transactions
are executed in parallel in different banks, as it independently
monitors the commands and signals to every bank and each
bank state on every clock cycle. Our generic power equations
can hence be employed individually for every transaction, thus
arriving at transaction-accurate power estimates. It should also
be noted that Micron’s power model is directly applicable only
when a single SDRAM bank is accessed, whereas our generic
model can be applied with any degree of bank-parallelism.
Figure 3 depicts the actual timing values for the parameters in
Table I and the command and data transfer cycles for different
transactions based on different memory access policies.
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(a) No Activate - No Precharge (NANP)
new
new
new
(b) Activate - No Precharge (ANP)
new
new
new
(c) No Activate - Precharge (NAP)
tRC
new
tRAS
new
tRCD
new
tRP
new
(d) Activate - Precharge (AP)
Fig. 3. Actual Timing Parameters for different transaction types
As indicated in Figure 3, these transactions differ in their
usage of activates and precharges as per the different policies:
(1) NANP: No Activate and no Precharge (Figure 3(a)),
because the last and the next transactions are to the same row
in the same bank as the current transaction.
(2) ANP: An Activate but no Precharge (Figure 3(b)),
because the last transaction precharged the bank and the next
transaction is to the same row in the same bank as the current.
(3) NAP: No Activate but a Precharge (Figure 3(c)), because
last transaction was to the same row in the same bank as the
current and the next is to a different row in the same bank.
(4) AP: Both an Activate and a Precharge (Figure 3(d)),
because the last and the next transactions are to a different
row in the same bank.
In a nutshell, our approach addresses state transitions,
employs actual timings between commands and is applicable
to all memory controller policies. Our approach adheres to
JEDEC specifications for current and timings and we derive
our power model on the logical basis of this approach.
V. B
ASIC SDRAM POWER MODEL
Micron has identified the basic power components that
add up and contribute to overall memory power consump-
tion [1]. These basic components include background power
components (contributing mainly to static power consump-
tion), such as Active Background (Act
BG
) and Precharged
Background (Pre
BG
) power, and active power components
(contributing mainly to dynamic power consumption), such
as Activate (ACT), Precharge (PRE), Read (RD), Write (WR)
and Refresh (REF) power. Unfortunately, Micron employs
the minimal constraints (issue (2) raised in Section I) to
calculate power consumption of these basic components. In
this section, we present alternatives to Micron’s equations
for these basic power components, considering the actual
timings between commands. In V-A, we cover the background
power components, in V-B, we detail power consumption of
ACT and PRE commands and in V-C and V-D, we derive
equations to provide power consumption of read, write and
refresh commands. In V-E, we discuss the auxiliary power
components that correspond to every read and write command,
including the ‘I/O’ power and the ‘Termination’ power. In V-F,
we provide a generic equation that combines all the basic
power components to compute power estimates for a trace of
any length from a single transaction to an entire application.
A general rule of thumb is that the background power com-
ponents (static power elements) scale up with increase in the
timing parameters, since they are always consumed whenever
the memory is ‘ON’ (leakage). On the other hand, the active
power components (dynamic power elements) scale down with
increase in timing parameters, since they contribute to power
consumption only for the period when they are used (based
on the switching activity), and get averaged over the actual
transaction length (tRC
new
). The basic power components that
add up for a sample read transaction with burst length 8 (using
a close-page policy) are shown in Figure 4. The clock cycles
in which they are consumed are indicated by ‘X’, for instance,
P(RD) is consumed over 4 cycles of data transfer.
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Fig. 4. Basic Power Components in a Read Transaction
A. Background Power
If all memory banks are in the precharged stand-by state,
the memory consumes a precharge background current (static
power component) of I
DD2N
[16]. However, even if a single
bank is in the active state, the memory consumes an active
background current (also static power component) of I
DD3N
.
Using these current specifications with the actual timings,
if a bank stays in the active state for a period of tRAS
new
cycles out of the total transaction length of tRC
new
cycles, it
consumes an average P (Act
BG
) static power per cycle for the
entire transaction length, as shown in Equation (1). If on the
other hand, all the banks remain in the precharged state for
tRP
new
cycles, the memory consumes an average P (Pre
BG
)
static power per cycle, given by Equation (2) for the entire
transaction length.
P (Act
BG
)=
tRAS
new
n=1
I
DD3N
× V
DD
/tRC
new
(1)
P (Pre
BG
)=
tRP
new
n=1
I
DD2N
× V
DD
/tRC
new
(2)
As shown in Equations (1) and (2), to estimate these power
values for any given transaction length tRC
new
, the power
consumption due to these background power components is
scaled over the transaction length. These actual timings can
be derived from a command trace by calculating the duration
for which any of the banks is in the active state, and for which
all the banks are in the precharged standby state.
B. Activate and Precharge Command Power
I
DD0
is specified as the average current consumed by the
memory when it executes an ACT command (to transfer the
data from the memory array to the row buffer) and a PRE
command (to charge the bit lines and restore the row buffer
contents back to the memory array), within the minimum
timing constraints. The I
DD0
current value also includes the
active background current I
DD3N
for the minimum period for
which the row is active (tRAS) and the precharge current I
DD2N
for the minimum period for which the row is precharged (tRC
- tRAS). Hence, these should be subtracted from I
DD0
for
the appropriate durations and averaged over the transaction
length tRC
new
to identify the average power consumed only
due to the ACT and PRE commands. The unmodified Micron
power model specifies these two power components as one,
assuming by default, a close-page policy. However, we split
them as P(ACT) and P(PRE) and provide estimates by using
the same total average current of I
DD0
and apply it separately
to the two components, based on the ratio of the number of
active cycles to precharge cycles in the transaction, as shown in
Equations (3) and (4), respectively. This partitioning enables us
to provide power estimates when using the open-page policy.
P (ACT)=
tRAS
n=1
(I
DD0
−I
DD3N
) × V
DD
/tRC
new
(3)
P (PRE)=
tRC
n=tRAS+1
(I
DD0
−I
DD2N
) × V
DD
/tRC
new
(4)
C. Read and Write Command Power
A Read command consumes I
DD4R
average current during
the cycles of the data transfer, while a Write command con-
sumes I
DD4W
. Since these also include the active background
current values consumed during the read or the write, I
DD3N
must be subtracted from the I
DD4R
and I
DD4W
currents, to
identify the power associated only with the Read and the Write
commands, respectively. To calculate the power associated
with the Read and Write commands, we first sum the current
values over the number of cycles the data is on the data bus
when reading from or writing to the SDRAM, identified here
using tR and tW, respectively. These cycles of data transfer for
a single burst of data can are be derived using the ratio of burst
length (BL) to data rate (DR). For DDR memories this equates
to BL/2. The power values are scaled over the transaction
length tRC
new
to get the average power consumed by a Read
and a Write, given by Equations (5) and (6), respectively.
P (RD)=
tR
n=1
(I
DD4R
− I
DD3N
) × V
DD
/tRC
new
(5)
P (WR)=
tW
n=1
(I
DD4W
− I
DD3N
) × V
DD
/tRC
new
(6)
D. Refresh Power
A refresh operation is used to retain the data in the SDRAM
by recharging the capacitors in the memory cells. A refresh
can be executed only when all the banks of the memory are
in the precharged state. A refresh thus consists of a single
Refresh command along with a set of pre-refresh NOPs that
gives enough time (at least tRP cycles) to precharge all the
banks each before executing the refresh. If all the banks all
already in the precharged idle state or the last command
of the last transaction was issued with an auto-precharge,
since the refresh would start only at the end of the auto-
precharge of the last transaction, no explicit precharges will
be required. Accordingly, P(PRE) (Equation (4)) is consumed
(with a transaction length of tRP) for the number of precharges
(N(PRE)) issued and I
DD2N
current is consumed for the tRP
cycles associated with those Precharges. Micron’s model fails
to consider the power consumed during pre-refresh clock
cycles, as a part of refresh power (issue (4) raised in Section I).
The refresh command by itself, consumes I
DD5
current over
the refresh cycles (tRFC). The refresh and pre-refresh power
components add up over tREF (=tRP+tRFC) cycles to give
the total refresh power, as shown in Equation (7).
P (REF)=
tRP
n=1
I
DD2N
× V
DD
+
N(PRE) × P (PRE)
/tREF
+
tRFC
n=1
I
DD5
×V
DD
/tREF (7)
E. Auxiliary Power Components
Besides these basic power components, other auxiliary
power components are associated with every read and write
operation. When a write is issued, the external signal used to
drive the data to the memory needs to be terminated on the
memory module to avoid distortions of other signals on the
