Proceedings ArticleDOI
Low power single bitline 6T SRAM cell with high read stability
Budhaditya Majumdar,Sumana Basu +1 more
- pp 169-174
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TLDR
This paper presents a novel CMOS 6-transistor SRAM cell for different purposes including low power embedded SRAM applications and stand-aloneSRAM applications that uses a single bit-line for both read and write purposes.Abstract:
This paper presents a novel CMOS 6-transistor SRAM cell for different purposes including low power embedded SRAM applications and stand-alone SRAM applications. The data is retained by the cell with the help of leakage current and positive feedback, and does not use any refresh cycle. The size of the new cell is comparable to the conventional six-transistor cell of same technology and design rules. Also, the proposed cells uses a single bit-line for both read and write purposes.read more
Citations
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Journal ArticleDOI
Design and performance analysis of 6T SRAM cell on different CMOS technologies with stability characterization
Shikha Saun,Hemant Kumar +1 more
Proceedings Article
A 0.6 V Dual-Rail Compiler SRAM Design on 45 nm CMOS Technology With Adaptive SRAM Power for Lower VDD_min VLSIs
Yen Huei Chen,Gary Chan,Shao Yu Chou,Pan Hsien-Yu,Jui-Jen Wu,Robin Lee,H. J. Liao,Hiroyuki Yamauchi +7 more
TL;DR: A 0.6 V 45 nm dual-rail SRAM design utilizing an adaptive voltage regulator targeted for the SRAM compiler application is proposed for the first time, and the bit-line (BL) is precharged to VDD instead of CVDD.
Proceedings ArticleDOI
Design of low power stable SRAM cell
TL;DR: In this paper, a nine transistors SRAM cell was proposed to reduce the static power and total power dissipation in a 250-nm CMOS technology, where three extra transistors were added to the conventional six transistors cell.
Proceedings ArticleDOI
VLSI design of low power SRAM architectures for FPGAs
Chakka Sri Harsha Kaushik,Rajiv Reddy Vanjarlapati,Varada Murali Krishna,Tadavarthi Gautam,V. Elamaran +4 more
TL;DR: In this article, different architectures of low power SRAM cells are compared with respect to parameters such as data retention stability, area, power dissipation, feature size, and memory capacity.
Journal ArticleDOI
Advances on Low Power Designs for SRAM Cell
Labonnah Farzana Rahman,Mohammad F. B. Amir,Mamun Bin Ibne Reaz,Mohd. Marufuzzaman,Hafizah Husain +4 more
TL;DR: In this paper, the authors reviewed and discussed several methods to overcome the power dissipation problem of SRAM and gave some idea for future research to improve the design of low power SRAM cell.
References
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TL;DR: Process, voltage and temperature variations; and their impact on circuit and microarchitecture; and possible solutions to reduce the impact of parameter variations and to achieve higher frequency bins are presented.
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Static-noise margin analysis of MOS SRAM cells
TL;DR: In this article, the stability of both resistor-load (R-load) and full-CMOS SRAM cells is investigated analytically as well as by simulation, and explicit analytic expressions for the static-noise margin (SNM) as a function of device parameters and supply voltage are derived.
Journal ArticleDOI
The impact of intrinsic device fluctuations on CMOS SRAM cell stability
TL;DR: In this paper, the reduction in CMOS SRAM cell static noise margin due to intrinsic threshold voltage fluctuations in uniformly doped minimum-geometry cell MOSFETs is investigated using compact physical and stochastic models.
Proceedings ArticleDOI
Stable SRAM cell design for the 32 nm node and beyond
Leland Chang,David M. Fried,John M. Hergenrother,Jeffrey W. Sleight,R.H. Dennard,Robert K. Montoye,Lidija Sekaric,Sharee J. McNab,Anna W. Topol,C.D. Adams,Kathryn W. Guarini,Wilfried Haensch +11 more
TL;DR: This work demonstrates the smallest 6T and full 8T-SRAM cells to date and provides a much greater enhancement in stability by eliminating cell disturbs during a read access, thus facilitating continued technology scaling.
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