Open AccessBook
Mosfet Modeling with Spice: Principles and Practice
TLDR
The SPICE Modeling and the Dominance of CMOS Technology and the Formalism of Model Building and the Future of Device Models for Circuit Simulation are studied.Abstract:
1. SPICE Modeling and the Dominance of CMOS Technology. 2. SPICE Modeling and the Formalism of Model Building. 3. The Semiconductor Physics of MOS Structures. 4. A Comparison of Analytical and Numerical Results. 5. The Level 1 Model. 6. The Level 2 Model. 7. The Level 3 Model. 8. BSIM. 9. HSPICE Level 28. 10. BSIM2. 11. BSIM3. 12. MOS Model 9. 13. The Active Device Capacitance. 14. Accounting for Systematic Process Variations. 15. Circuit Level Correlation of Models and Hardware. 16. New Model Candidates. 17. The Future of Device Models for Circuit Simulation. APPENDICES. A. An Executive Summary of the Various Models. B. Channel Length and Width. C. The Final Model Equations. D. The Extracted HSPICE Level 28 Model. E. The Binned BSIM2 Model. INDEX.read more
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Journal ArticleDOI
Circuit techniques for reducing the effects of op-amp imperfections: autozeroing, correlated double sampling, and chopper stabilization
Christian Enz,Gabor C. Temes +1 more
TL;DR: In this paper, some old and new circuit techniques are described for the compensation of the amplifier's most important nonideal effects including the noise (mainly thermal and 1/f noise), the input-referred dc offset voltage as well as the finite gain.
Journal ArticleDOI
PSP: An Advanced Surface-Potential-Based MOSFET Model for Circuit Simulation
G. Gildenblat,Xin Li,W. Wu,H. Wang,Amit Jha,R. van Langevelde,G.D.J. Smit,A.J. Scholten,D.B.M. Klaassen +8 more
TL;DR: In this paper, the authors describe the latest and most advanced surface potential-based model jointly developed by The Pennsylvania State University and Philips, which includes model structure, mobility and velocity saturation description, further development and verification of symmetric linearization method, recent advances in the computational techniques for the surface potential, modeling of gate tunneling current, inclusion of the retrograde impurity profile, and noise sources.
Journal ArticleDOI
Process and temperature compensation in a 7-MHz CMOS clock oscillator
TL;DR: The design and characterization of a process, temperature and supply compensation technique for a 7-MHz clock oscillator in a 0.25-/spl mu/m, two-poly five-metal (2P5M) CMOS process is reported.
Journal ArticleDOI
Revisiting MOSFET threshold voltage extraction methods
Adelmo Ortiz-Conde,Francisco J. García-Sánchez,Juan Muci,Alberto Terán Barrios,Juin J. Liou,Juin J. Liou,Ching-Sung Ho +6 more
TL;DR: An up-to-date review of the several extraction methods commonly used to determine the value of the threshold voltage of MOSFETs, which includes the different methods that extract this quantity from the drain current versus gate voltage transfer characteristics measured under linear operation conditions for crystalline and non-crystalline MOSfETs.
Process and Temperature Compensation in a 7-MHz
TL;DR: In this article, the design and characterization of a process, temperature and supply compensation technique for a 7-MHz clock oscillator in a 0.25-m, two-poly five-metal (2P5M) CMOS process is described.