Journal ArticleDOI
Processing and Prolonged 500 C Testing of 4H-SiC JFET Integrated Circuits with Two Levels of Metal Interconnect
David J. Spry,Philip G. Neudeck,Liang-Yu Chen,Dorothy Lukco,Carl W. Chang,Glenn M. Beheim,Michael J. Krasowski,Norman F. Prokop +7 more
TLDR
In this article, the authors report the processing and testing of 4H-SiC junction field effect transistor (JFET) prototype IC's with two levels of metal interconnect capable of prolonged operation at 500 C.Abstract:
Complex integrated circuit (IC) chips rely on more than one level of interconnect metallization for routing of electrical power and signals. This work reports the processing and testing of 4H-SiC junction field effect transistor (JFET) prototype IC's with two levels of metal interconnect capable of prolonged operation at 500 C. Packaged functional circuits including 3- and 11-stage ring oscillators, a 4-bit digital to analog converter, and a 4-bit address decoder and random access memory cell have been demonstrated at 500 C. A 3-stage oscillator functioned for over 3000 hours at 500 C in air ambient. Improved reproducibility remains to be accomplished.read more
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Journal ArticleDOI
Demonstration of 4H-SiC Digital Integrated Circuits Above 800 °C
TL;DR: In this paper, short-term demonstrations of packaged 4H-SiC junction field effect transistor (JFET) logic integrated circuits (ICs) at temperatures exceeding 800 °C in air are reported, including a 26-transistor 11-stage ring oscillator that functioned at 961 °C ambient temperature.
Journal ArticleDOI
Prolonged 500 °C Demonstration of 4H-SiC JFET ICs With Two-Level Interconnect
TL;DR: In this paper, fabrication and testing of integrated circuits (ICs) with two levels of interconnect that consistently achieve greater than 1000 h of stable electrical operation at 500 °C in air ambient.
Journal ArticleDOI
Operational Testing of 4H-SiC JFET ICs for 60 Days Directly Exposed to Venus Surface Atmospheric Conditions
Philip G. Neudeck,Liang-Yu Chen,Roger D. Meredith,Dorothy Lukco,David J. Spry,Leah M. Nakley,Gary W. Hunter +6 more
TL;DR: In this paper, the authors report a successful two-month (60-day) operational demonstration of two 175-transistor 4H-SiC junction field effect transistor (JFET) integrated circuits directly exposed (no cooling and no protective chip packaging) to high-fidelity physical and chemical reproduction of Venus surface atmospheric conditions in a test chamber.
Journal ArticleDOI
High-Temperature Operation of Silicon Carbide CMOS Circuits for Venus Surface Application
TL;DR: In this paper, the results of elevated temperature testing (as high as 500°C) for extended periods (up to 100 hours) of several building block circuits were presented, created using the Raytheon UK's HiTSiC® CMOS process, present the densest, lowest power integrated circuit technology capable of operating at these extreme temperatures for any period of time.
Journal ArticleDOI
Yearlong 500 °C Operational Demonstration of Up-scaled 4H-SiC JFET Integrated Circuits
Philip G. Neudeck,David J. Spry,Michael J. Krasowski,Norman F. Prokop,Glenn M. Beheim,Liang-Yu Chen,Carl W. Chang +6 more
TL;DR: In this paper, the first stable electrical operation of semiconductor ICs for 1 year (8760 hours) at 500°C in air atmosphere was reported, achieving a more than 7-fold increase in circuit complexity from the 24 transistor ring oscillator ICs reported at HiTEC 2016.