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Open AccessJournal ArticleDOI

Rediscovering Majority Logic in the Post-CMOS Era: A Perspective from In-Memory Computing

John Reuben
- 04 Sep 2020 - 
- Vol. 10, Iss: 3, pp 28
TLDR
In this review, memristive logic families which can implement MAJORITY gate and NOT are to be favored for in-memory computing, and one-bit full adders implemented in memory array using different logic primitives are compared and the efficiency of majority-based implementation is underscores.
Abstract
As we approach the end of Moore’s law, many alternative devices are being explored to satisfy the performance requirements of modern integrated circuits. At the same time, the movement of data between processing and memory units in contemporary computing systems (‘von Neumann bottleneck’ or ‘memory wall’) necessitates a paradigm shift in the way data is processed. Emerging resistance switching memories (memristors) show promising signs to overcome the ‘memory wall’ by enabling computation in the memory array. Majority logic is a type of Boolean logic which has been found to be an efficient logic primitive due to its expressive power. In this review, the efficiency of majority logic is analyzed from the perspective of in-memory computing. Recently reported methods to implement majority gate in Resistive RAM array are reviewed and compared. Conventional CMOS implementation accommodated heterogeneity of logic gates (NAND, NOR, XOR) while in-memory implementation usually accommodates homogeneity of gates (only IMPLY or only NAND or only MAJORITY). In view of this, memristive logic families which can implement MAJORITY gate and NOT (to make it functionally complete) are to be favored for in-memory computing. One-bit full adders implemented in memory array using different logic primitives are compared and the efficiency of majority-based implementation is underscored. To investigate if the efficiency of majority-based implementation extends to n-bit adders, eight-bit adders implemented in memory array using different logic primitives are compared. Parallel-prefix adders implemented in majority logic can reduce latency of in-memory adders by 50–70% when compared to IMPLY, NAND, NOR and other similar logic primitives.

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Citations
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Journal ArticleDOI

Accelerated Addition in Resistive RAM Array Using Parallel-Friendly Majority Gates

TL;DR: A method to implement a majority gate in a transistor-accessed ReRAM array during the READ operation, which forms a functionally complete Boolean logic, capable of implementing any digital logic.
Posted Content

Highly Non-linear and Reliable Amorphous Silicon Based Back-to-Back Schottky Diode as Selector Device for Large Scale RRAM Arrays

TL;DR: In this article, the authors present silicon process compatible, stable and reliable back-to-back Schottky diodes with high nonlinearity ratio at half-read voltage, high speed and low operating voltage.
Journal ArticleDOI

Unlocking approximation for in-memory computing with Cartesian genetic programming and computer algebra for arithmetic circuits

Saman Froehlich, +1 more
- 16 Feb 2022 - 
TL;DR: This article extends existing compilation techniques for the Programmable Logic in-Memory (PLiM) computer architecture, by adapting state-of-the-art approximate computing techniques for arithmetic circuits by using Cartesian Genetic Programming and a Symbolic Computer Algebra-based technique with respect to error-metrics.
Journal ArticleDOI

Novel In-Memory Computing Adder Using 8+T SRAM

Soon Yong Song, +1 more
- 16 Mar 2022 - 
TL;DR: According to the performance in this study, the 8+T SRAM IMC circuit, proposed FA, proposed RCA, and proposed approximated adder are good candidates for IMC, which aims to reduce energy consumption and improve overall performance.
Journal ArticleDOI

Multi-Input Logic-in-Memory for Ultra-Low Power Non-Von Neumann Computing.

TL;DR: In this article, a multi-input logic operation implemented on a smart logic-in-memory (SIMPLY) architecture is presented, which improves the circuit reliability and reduces energy consumption.
References
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Journal ArticleDOI

‘Memristive’ switches enable ‘stateful’ logic operations via material implication

TL;DR: Bipolar voltage-actuated switches, a family of nonlinear dynamical memory devices, can execute material implication (IMP), which is a fundamental Boolean logic operation on two variables p and q such that pIMPq is equivalent to (NOTp)ORq.
Journal ArticleDOI

In-memory computing with resistive switching devices

TL;DR: This Review Article examines the development of in-memory computing using resistive switching devices, where the two-terminal structure of the devices, theirresistive switching properties, and direct data processing in the memory can enable area- and energy-efficient computation.
Journal ArticleDOI

New Conduction and Reversible Memory Phenomena in Thin Insulating Films

TL;DR: In this paper, it is assumed that the injected ions introduce a broad band of localized impurity levels within the normally forbidden band of the insulator, and that the electrons can, under certain conditions, be trapped within the impurity band.
Journal ArticleDOI

Memristor-Based Material Implication (IMPLY) Logic: Design Principles and Methodologies

TL;DR: The IMPLY logic gate, a memristor-based logic circuit, is described and a methodology for designing this logic family is proposed, based on a general design flow suitable for all deterministic memristive logic families.
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