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Journal ArticleDOI

Reset-Free Memoryless Delta–Sigma Analog-to-Digital Conversion

TLDR
It is shown that memoryless A/D conversion without reset can be realized using a discrete-time DSM with a signal transfer function (STF) of unity and a Nyquist -band decimation filter running at the oversampled rate.
Abstract
This paper presents new techniques to obtain sample-by-sample analog-to-digital conversion using a delta–sigma modulator (DSM) without resetting the modulator or the decimation filter. It is shown that memoryless A/D conversion without reset can be realized using a discrete-time DSM with a signal transfer function (STF) of unity and a Nyquist $M$ -band decimation filter running at the oversampled rate. It is also shown that a delta–sigma ADC preceded by a sample-and-hold at the Nyquist rate is a linear, time-invariant system at the Nyquist rate. This relaxes the constraint on the STF and allows using a multi-rate decimation filter and an equalizer at the Nyquist rate to significantly lower the power in the digital filters. Crosstalk suppression, which is limited by analog imperfections when a fixed-coefficient equalizer is used, is shown to be substantially improved using an adaptive equalizer at the Nyquist rate. A 180-nm prototype operating at 32 MHz and an OSR of 32 demonstrates two-channel operation with crosstalk below 89 dB. It consumes 18.2 mA from a 1.8-V supply, occupies 3.86 mm2 and has DR/SNR/SNDR of 84.2/82.5/80.1 dB.

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Citations
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Journal ArticleDOI

Multi-Channel Analog-to-Digital Conversion Techniques Using a Continuous-Time Delta-Sigma Modulator Without Reset

TL;DR: Two methods are presented for implementing a multi-channel ADC using a continuous-time delta-sigma modulator (CTDSM) without resetting its states and an adaptive equalizer used for flattening the equivalent frequency response and eliminate memory.
Posted ContentDOI

Soft-Core Architecture for Odd/Even Order Sampling I/Q Demodulator with Dual-Port Block Memory Considerations

TL;DR: This paper proposes a third-generation piecewise sampling with soft-core architecture that enables an option to select both odd and even while interfacing to memory mapping, and has superior SNR performance.
Journal ArticleDOI

Odd/Even Order Sampling Soft-Core Architecture Towards Mixed Signals Fourth Industrial Revolution (4IR) Applications

TL;DR: A performance study of three sampling techniques: the proposed new and novel odd/even order sampling architecture, existing Mod-∆, and traditional 1st order delta-sigma, to address the efficiency of a digital interface with a 4IR platform.
Journal ArticleDOI

Improved Acquisition System for Sensored Vector Control Through Frequency-Domain Multiplexing, Synchronous Sampling, and Differential Evolution

TL;DR: In this paper, an improvement of the FDM-based acquisition system through synchronous sampling and differential evolution (DE) is proposed, which allows an accurate estimation of the current fundamental components and the angular position when FDM is used, with better performance respect to other approaches in the literature.
References
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Journal ArticleDOI

An economical class of digital filters for decimation and interpolation

TL;DR: A class of digital linear phase finite impulse response (FIR) filters for decimation and interpolation and use limited storage making them an economical alternative to conventional implementations for certain applications.
Journal ArticleDOI

Signed-Digit Numbe Representations for Fast Parallel Arithmetic

TL;DR: Sign-digit representations limit carry-propagation to one position to the left during the operations of addition and subtraction in digital computers and arithmetic operations with signed-digit numbers: addition, subtraction, multiplication, division and roundoff are discussed.
Journal ArticleDOI

A 3-V 340-mW 14-b 75-Msample/s CMOS ADC with 85-dB SFDR at Nyquist input

TL;DR: The ADC uses a 4-b first stage to relax capacitor-matching requirements, buffered bootstrapping to reduce signal-dependent charge injection, and a flip-around track-and-hold amplifier with wide common-mode compliance to reduce noise and power consumption to achieve 14-b accuracy without calibration or dithering.
Journal ArticleDOI

Theory and applications of incremental /spl Delta//spl Sigma/ converters

TL;DR: It is shown how speed, resolution, and A/D complexity can be optimized for a given design, and how with some special digital filters improved speed/resolution ratio can be achieved.
Journal ArticleDOI

Design-oriented estimation of thermal noise in switched-capacitor circuits

TL;DR: A tutorial description of the physical phenomena taking place in an SC circuit while it processes noise is provided and some specialized but highly efficient algorithms for estimating the resulting sampled noise in SC circuits are proposed, which need only simple calculations.
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